mb/google/hatch: Enable PCIe WLAN and BT

Enable PCIe WLAN for hatch
1. Enable PCI port 14 for PCIe WLAN
2. Enable CLKREQ, CLK SRC 3 for PCI port 14
3. GPIO pad config for WLAN and BT
USB port for BT has already been enabled so not included in this patch

BUG=b:120914069
BRANCH=none
TEST=check if code compiles correctly and verify GPIO configuration with
schematics

Change-Id: I4f2a6eb37a467ad8b8cdde8fe6b657fabb383b04
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/30467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>

src/mainboard/google/hatch/variants/baseboard/devicetree.cb

@@ -5,6 +5,7 @@ chip soc/intel/cannonlake
 	# route. i.e. If this route changes then the affected GPE
 	# offset bits also need to be changed.
 	# DW1 is used by:
+	#   - GPP_C1  - PCIE_14_WLAN_WAKE_ODL
 	#   - GPP_C21 - H1_PCH_INT_ODL
 	register "gpe0_dw0" = "PMC_GPP_A"
 	register "gpe0_dw1" = "PMC_GPP_C"
@@ -83,6 +84,12 @@ chip soc/intel/cannonlake
 	# GPIO for SD card detect
 	register "sdcard_cd_gpio" = "GPP_G5"
 
+	# PCIe port 14 for M.2 E-key WLAN
+	register "PcieRpEnable[13]" = "1"
+	# RP 14 uses CLK SRC 3
+	register "PcieClkSrcUsage[3]" = "13"
+	register "PcieClkSrcClkReq[3]" = "3"
+
 	device cpu_cluster 0 on
 		device lapic 0 on end
 	end
@@ -225,7 +232,13 @@ chip soc/intel/cannonlake
 		device pci 1d.1 off end # PCI Express Port 10
 		device pci 1d.2 off end # PCI Express Port 11
 		device pci 1d.3 off end # PCI Express Port 12
-		device pci 1d.4 off end # PCI Express Port 13 (x4)
+		device pci 1d.4 off end # PCI Express port 13
+		device pci 1d.5 on
+			chip drivers/intel/wifi
+				register "wake" = "GPE0_DW1_01"
+				device pci 00.0 on  end
+			end
+		end # PCI Express Port 14 (x4)
 		device pci 1e.0 on  end # UART #0
 		device pci 1e.1 off end # UART #1
 		device pci 1e.2 on

src/mainboard/google/hatch/variants/baseboard/gpio.c

@@ -27,6 +27,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_APIC(GPP_A21, NONE, PLTRST, LEVEL, INVERT),
 	/* SRCCLKREQ1 */
 	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
+	/* PCIE_14_WLAN_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
 	/* H1_SLAVE_SPI_CS_L */
 	PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
 	/* H1_SLAVE_SPI_CLK */
@@ -37,10 +39,14 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
 	/* TOUCHSCREEN_DIS_L */
 	PAD_CFG_GPO(GPP_C4, 0, DEEP),
-	/* GPP_C11_TP => NC */
+	/* PCIE_14_WLAN_WAKE_ODL */
-	PAD_NC(GPP_C11, DN_20K),
+	PAD_CFG_GPI_SCI_LOW(GPP_C1, NONE, DEEP, EDGE_SINGLE),
-	/* GPP_C10_TP => NC */
+	/* GPP_C10_TP */
 	PAD_NC(GPP_C10, DN_20K),
+	/* GPP_C11_TP */
+	PAD_NC(GPP_C11, DN_20K),
+	/* BT_DISABLE_L */
+	PAD_CFG_GPO(GPP_C14, 1, DEEP),
 	/* PCH_I2C_TRACKPAD_SDA */
 	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
 	/* PCH_I2C_TRACKPAD_SCL */
@@ -55,6 +61,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, INVERT),
 	/* EC_IN_RW_OD */
 	PAD_CFG_GPI(GPP_C22, NONE, DEEP),
+	/* WLAN_PE_RST# */
+	PAD_CFG_GPO(GPP_C23, 1, DEEP),
 	/* TOUCHSCREEN_RST_L */
 	PAD_CFG_GPO(GPP_D15, 0, DEEP),
 	/* TOUCHSCREEN_INT_L */
@@ -135,6 +143,8 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
 	/* H1_PCH_INT_ODL */
 	PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, INVERT),
+	/* WLAN_PE_RST# */
+	PAD_CFG_GPO(GPP_C23, 1, DEEP),
 };
 
 const struct pad_config *__weak variant_early_gpio_table(size_t *num)