From 6237175ed5ef29a0e9b82cc7268ca424c5bb44ea Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 27 Mar 2021 21:13:44 +0100 Subject: [PATCH] nb/intel/haswell: Uniformize include guards Remove leading and trailing underscores and change `RAMINIT_H` to be more consistent with other headers. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: Ie20fcaa0f9393eb0a34054eda53b9bade63cc0d2 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/51890 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/haswell.h | 6 +++--- src/northbridge/intel/haswell/memmap.h | 6 +++--- src/northbridge/intel/haswell/raminit.h | 6 +++--- src/northbridge/intel/haswell/registers/dmibar.h | 6 +++--- src/northbridge/intel/haswell/registers/epbar.h | 6 +++--- src/northbridge/intel/haswell/registers/host_bridge.h | 6 +++--- src/northbridge/intel/haswell/registers/mchbar.h | 6 +++--- 7 files changed, 21 insertions(+), 21 deletions(-) diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index b010cdfbd0..6faf78798c 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ -#define __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ +#ifndef NORTHBRIDGE_INTEL_HASWELL_HASWELL_H +#define NORTHBRIDGE_INTEL_HASWELL_HASWELL_H #include #include @@ -68,4 +68,4 @@ struct acpi_rsdp; unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long start, struct acpi_rsdp *rsdp); -#endif /* __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ */ +#endif /* NORTHBRIDGE_INTEL_HASWELL_HASWELL_H */ diff --git a/src/northbridge/intel/haswell/memmap.h b/src/northbridge/intel/haswell/memmap.h index 02bdecc38a..1aa2d675a6 100644 --- a/src/northbridge/intel/haswell/memmap.h +++ b/src/northbridge/intel/haswell/memmap.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H__ -#define __NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H__ +#ifndef NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H +#define NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H #define GFXVT_BASE_ADDRESS 0xfed90000ULL #define GFXVT_BASE_SIZE 0x1000 @@ -9,4 +9,4 @@ #define VTVC0_BASE_ADDRESS 0xfed91000ULL #define VTVC0_BASE_SIZE 0x1000 -#endif /* __NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H__ */ +#endif /* NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H */ diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h index 5483229f3b..e151b46d8b 100644 --- a/src/northbridge/intel/haswell/raminit.h +++ b/src/northbridge/intel/haswell/raminit.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef NORTHBRIDGE_INTEL_HASWELL_RAMINIT_H +#define NORTHBRIDGE_INTEL_HASWELL_RAMINIT_H #include @@ -17,4 +17,4 @@ void mb_get_spd_map(struct spd_info *spdi); void perform_raminit(const int s3resume); -#endif /* RAMINIT_H */ +#endif /* NORTHBRIDGE_INTEL_HASWELL_RAMINIT_H */ diff --git a/src/northbridge/intel/haswell/registers/dmibar.h b/src/northbridge/intel/haswell/registers/dmibar.h index 9d523825a7..09a9078353 100644 --- a/src/northbridge/intel/haswell/registers/dmibar.h +++ b/src/northbridge/intel/haswell/registers/dmibar.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __HASWELL_REGISTERS_DMIBAR_H__ -#define __HASWELL_REGISTERS_DMIBAR_H__ +#ifndef HASWELL_REGISTERS_DMIBAR_H +#define HASWELL_REGISTERS_DMIBAR_H #define DMIVCECH 0x000 /* 32bit */ #define DMIPVCCAP1 0x004 /* 32bit */ @@ -53,4 +53,4 @@ #define DMI_AFE_PM_TMR 0xc28 /* 32bit */ -#endif /* __HASWELL_REGISTERS_DMIBAR_H__ */ +#endif /* HASWELL_REGISTERS_DMIBAR_H */ diff --git a/src/northbridge/intel/haswell/registers/epbar.h b/src/northbridge/intel/haswell/registers/epbar.h index 699a2ba578..cccfcca642 100644 --- a/src/northbridge/intel/haswell/registers/epbar.h +++ b/src/northbridge/intel/haswell/registers/epbar.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __HASWELL_REGISTERS_EPBAR_H__ -#define __HASWELL_REGISTERS_EPBAR_H__ +#ifndef HASWELL_REGISTERS_EPBAR_H +#define HASWELL_REGISTERS_EPBAR_H #define EPPVCCAP1 0x004 /* 32bit */ #define EPPVCCAP2 0x008 /* 32bit */ @@ -25,4 +25,4 @@ #define EPLE4D 0x080 /* 32bit */ #define EPLE4A 0x088 /* 64bit */ -#endif /* __HASWELL_REGISTERS_EPBAR_H__ */ +#endif /* HASWELL_REGISTERS_EPBAR_H */ diff --git a/src/northbridge/intel/haswell/registers/host_bridge.h b/src/northbridge/intel/haswell/registers/host_bridge.h index 7746801804..1ee0ab2890 100644 --- a/src/northbridge/intel/haswell/registers/host_bridge.h +++ b/src/northbridge/intel/haswell/registers/host_bridge.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __HASWELL_REGISTERS_HOST_BRIDGE_H__ -#define __HASWELL_REGISTERS_HOST_BRIDGE_H__ +#ifndef HASWELL_REGISTERS_HOST_BRIDGE_H +#define HASWELL_REGISTERS_HOST_BRIDGE_H #define EPBAR 0x40 #define MCHBAR 0x48 @@ -71,4 +71,4 @@ #define CAPID0_B 0xe8 -#endif /* __HASWELL_REGISTERS_HOST_BRIDGE_H__ */ +#endif /* HASWELL_REGISTERS_HOST_BRIDGE_H */ diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h index 2dfad621f9..5610e7089a 100644 --- a/src/northbridge/intel/haswell/registers/mchbar.h +++ b/src/northbridge/intel/haswell/registers/mchbar.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __HASWELL_REGISTERS_MCHBAR_H__ -#define __HASWELL_REGISTERS_MCHBAR_H__ +#ifndef HASWELL_REGISTERS_MCHBAR_H +#define HASWELL_REGISTERS_MCHBAR_H /* Memory controller characteristics */ #define NUM_CHANNELS 2 @@ -74,4 +74,4 @@ #define CRDTLCK 0x77fc #define MCARBLCK 0x7ffc -#endif /* __HASWELL_REGISTERS_MCHBAR_H__ */ +#endif /* HASWELL_REGISTERS_MCHBAR_H */