soc/intel/skylake: devicetree: introduce PchHdaVcType fsp parameter

Make the the FSP Parameter PchHdaVcType a devicetree setting and make
use of it in the devicetrees of all boards that currently set it.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Ibafc3b6bd2495658f2bd634218042ec413a89f5e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
This commit is contained in:
Michael Niewöhner 2019-09-23 14:38:41 +02:00 committed by Patrick Georgi
parent 5387144a93
commit 6238563b2b
8 changed files with 12 additions and 8 deletions

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@ -55,6 +55,7 @@ chip soc/intel/skylake
register "PmTimerDisabled" = "0"
register "EnableAzalia" = "1"
register "DspEnable" = "0"
register "PchHdaVcType" = "Vc1"
register "pirqa_routing" = "PCH_IRQ11"
register "pirqb_routing" = "PCH_IRQ10"

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@ -24,6 +24,4 @@ void mainboard_silicon_init_params(FSP_SIL_UPD *params)
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
params->CdClock = 3;
/* Enable Virtual Channel 1 */
params->PchHdaVcType = 0x1;
}

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@ -25,9 +25,6 @@ void mainboard_silicon_init_params(FSP_SIL_UPD *params)
* dependencies during hardware initialization. */
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
params->CdClock = 3;
/* Enable Virtual Channel 1 */
params->PchHdaVcType = 0x1;
}
static void ioexpander_init(void *unused)

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@ -30,6 +30,7 @@ chip soc/intel/skylake
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
register "SaGv" = "SaGv_Enabled"
register "PchHdaVcType" = "Vc1"
register "pirqa_routing" = "PCH_IRQ11"
register "pirqb_routing" = "PCH_IRQ10"

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@ -20,7 +20,4 @@ void mainboard_silicon_init_params(FSP_SIL_UPD *params)
/* Configure pads prior to SiliconInit() in case there's any
* dependencies during hardware initialization. */
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
/* This must be one, otherwise FSP crashes ... */
params->PchHdaVcType = 0x1;
}

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@ -30,6 +30,9 @@ chip soc/intel/skylake
register "PcieRpEnable[8]" = "1"
register "PcieRpClkReqSupport[8]" = "0"
# FIXME: find out why FSP crashes without this
register "PchHdaVcType" = "Vc1"
device domain 0 on
device pci 01.0 on end # unused
device pci 01.1 on # PCIE Slot (JPCIE1)

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@ -208,6 +208,12 @@ struct soc_intel_skylake_config {
u8 EnableAzalia;
u8 DspEnable;
/* HDA Virtual Channel Type Select */
enum {
Vc0,
Vc1,
} PchHdaVcType;
/*
* I/O Buffer Ownership:
* 0: HD-A Link

View File

@ -361,6 +361,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PchIshEnable = dev ? dev->enabled : 0;
params->PchHdaEnable = config->EnableAzalia;
params->PchHdaVcType = config->PchHdaVcType;
params->PchHdaIoBufferOwnership = config->IoBufferOwnership;
params->PchHdaDspEnable = config->DspEnable;
params->Device4Enable = config->Device4Enable;