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src/soc/intel/braswell/include/soc/iomap.h: Correct IO_BASE_SIZE and ILB_BASE_SIZE 

The sizes of IO_BASE and ILB_BASE areas a incorrect.
Correct IO_BASE_SIZE and ILB_BASE_SIZE values.

BUG=N/A
TEST=Intel CherryHill CRB

Change-Id: I23c3fd608598c5ec2271d393168ac4bf406772b4
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Frans Hendriks 2018-10-31 13:50:10 +01:00 committed by Patrick Georgi
parent dcf52c87a6
commit 624195e454
1 changed files with 3 additions and 2 deletions
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5
src/soc/intel/braswell/include/soc/iomap.h
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@ -3,6 +3,7 @@
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015 Intel Corp.
* Copyright (C) 2018 Eltan B.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -35,7 +36,7 @@
/* IO Memory */
#define IO_BASE_ADDRESS 0xfed80000
#define IO_BASE_SIZE 0x4000
#define IO_BASE_SIZE 0x40000
#define COMMUNITY_OFFSET_GPSOUTHWEST 0x00000
#define COMMUNITY_OFFSET_GPNORTH 0x08000
#define COMMUNITY_OFFSET_GPEAST 0x10000
@ -43,7 +44,7 @@
/* Intel Legacy Block */
#define ILB_BASE_ADDRESS 0xfed08000
#define ILB_BASE_SIZE 0x400
#define ILB_BASE_SIZE 0x2000
/* SPI Bus */
#define SPI_BASE_ADDRESS 0xfed01000