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mb/emulation/qemu-q35: Convert to ASL 2.0 syntax 

Generated 'build/dsdt.dsl' files are identical.

Change-Id: I4e0f64def6c4c712793d3b2ede99dd74f9046fcb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46163
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS 2020-10-08 09:21:19 +02:00 committed by Patrick Georgi
parent fda6e6f305
commit 6245d076b9
1 changed files with 16 additions and 16 deletions
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32
src/mainboard/emulation/qemu-q35/dsdt.asl
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@ -46,31 +46,31 @@ DefinitionBlock (
CreateDWordField(Arg3, 0, CDW1) CreateDWordField(Arg3, 0, CDW1)
// Check for proper UUID // Check for proper UUID
If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) {
// Create DWORD-addressable fields from the Capabilities Buffer // Create DWORD-addressable fields from the Capabilities Buffer
CreateDWordField(Arg3, 4, CDW2) CreateDWordField(Arg3, 4, CDW2)
CreateDWordField(Arg3, 8, CDW3) CreateDWordField(Arg3, 8, CDW3)
// Save Capabilities DWORD2 & 3 // Save Capabilities DWORD2 & 3
Store(CDW2, SUPP) SUPP = CDW2
Store(CDW3, CTRL) CTRL = CDW3
// Always allow native PME, AER (no dependencies) // Always allow native PME, AER (no dependencies)
// Never allow SHPC (no SHPC controller in this system) // Never allow SHPC (no SHPC controller in this system)
And(CTRL, 0x1D, CTRL) CTRL &= 0x1D
If (LNotEqual(Arg1, One)) { If (Arg1 != 1) {
// Unknown revision // Unknown revision
Or(CDW1, 0x08, CDW1) CDW1 |= 0x08
} }
If (LNotEqual(CDW3, CTRL)) { If (CDW3 != CTRL) {
// Capabilities bits were masked // Capabilities bits were masked
Or(CDW1, 0x10, CDW1) CDW1 |= 0x10
} }
// Update DWORD3 in the buffer // Update DWORD3 in the buffer
Store(CTRL, CDW3) CDW3 = CTRL
} Else { } Else {
Or(CDW1, 4, CDW1) // Unrecognized UUID CDW1 |= 4 // Unrecognized UUID
} }
Return (Arg3) Return (Arg3)
} }
@ -145,7 +145,7 @@ DefinitionBlock (
/* Zero => PIC mode, One => APIC Mode */ /* Zero => PIC mode, One => APIC Mode */
Name(\PICF, Zero) Name(\PICF, Zero)
Method(\_PIC, 1, NotSerialized) { Method(\_PIC, 1, NotSerialized) {
Store(Arg0, \PICF) \PICF = Arg0
} }
Scope(\_SB) { Scope(\_SB) {
@ -269,7 +269,7 @@ DefinitionBlock (
section 6.2.8.1 */ section 6.2.8.1 */
/* Note: we provide the same info as the PCI routing /* Note: we provide the same info as the PCI routing
table of the Bochs BIOS */ table of the Bochs BIOS */
If (LEqual(\PICF, Zero)) { If (\PICF == 0) {
Return (PRTP) Return (PRTP)
} Else { } Else {
Return (PRTA) Return (PRTA)
@ -292,7 +292,7 @@ DefinitionBlock (
Method(IQST, 1, NotSerialized) { Method(IQST, 1, NotSerialized) {
// _STA method - get status // _STA method - get status
If (And(0x80, Arg0)) { If (0x80 & Arg0) {
Return (0x09) Return (0x09)
} }
Return (0x0B) Return (0x0B)
@ -303,7 +303,7 @@ DefinitionBlock (
Interrupt(, Level, ActiveHigh, Shared) { 0 } Interrupt(, Level, ActiveHigh, Shared) { 0 }
}) })
CreateDWordField(PRR0, 0x05, PRRI) CreateDWordField(PRR0, 0x05, PRRI)
Store(And(Arg0, 0x0F), PRRI) PRRI = Arg0 & 0x0F
Return (PRR0) Return (PRR0)
} }
@ -320,14 +320,14 @@ DefinitionBlock (
Return (IQST(reg)) \ Return (IQST(reg)) \
} \ } \
Method(_DIS, 0, NotSerialized) { \ Method(_DIS, 0, NotSerialized) { \
Or(reg, 0x80, reg) \ reg |= 0x80 \
} \ } \
Method(_CRS, 0, NotSerialized) { \ Method(_CRS, 0, NotSerialized) { \
Return (IQCR(reg)) \ Return (IQCR(reg)) \
} \ } \
Method(_SRS, 1, NotSerialized) { \ Method(_SRS, 1, NotSerialized) { \
CreateDWordField(Arg0, 0x05, PRRI) \ CreateDWordField(Arg0, 0x05, PRRI) \
Store(PRRI, reg) \ reg = PRRI \
} \ } \
} }