soc/intel/cannonlake: Fix GPIO reset mapping
According to document 337348-001 (Intel® 300 Series and Intel® C240 Series Chipset Family Platform Controller Hub Datasheet - Volume 2 of 2), the only GPIOs that support PWROK reset are those in the GPD group. The mappings themselves are correct, but they're assigned to the wrong communities. Change-Id: Ib586c987f768ddff31b053f4c108a8526326a7dc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69214 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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@ -11,7 +11,7 @@ static const struct reset_mapping rst_map[] = {
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{ .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
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};
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static const struct reset_mapping rst_map_com0[] = {
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static const struct reset_mapping rst_map_gpd[] = {
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{ .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
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{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
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{ .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
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@ -83,8 +83,8 @@ static const struct pad_community cnl_communities[] = {
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.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
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.name = "GPP_AB",
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.acpi_path = "\\_SB.PCI0.GPIO",
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.reset_map = rst_map_com0,
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.num_reset_vals = ARRAY_SIZE(rst_map_com0),
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.reset_map = rst_map,
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.num_reset_vals = ARRAY_SIZE(rst_map),
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.groups = cnl_community0_groups,
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.num_groups = ARRAY_SIZE(cnl_community0_groups),
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},
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@ -127,8 +127,8 @@ static const struct pad_community cnl_communities[] = {
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.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
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.name = "GPD",
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.acpi_path = "\\_SB.PCI0.GPIO",
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.reset_map = rst_map,
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.num_reset_vals = ARRAY_SIZE(rst_map),
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.reset_map = rst_map_gpd,
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.num_reset_vals = ARRAY_SIZE(rst_map_gpd),
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.groups = cnl_community2_groups,
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.num_groups = ARRAY_SIZE(cnl_community2_groups),
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},
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