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mb/google/zork: Drop RAM_ID configuration from romstage gpio table 

RAM_ID GPIOs are configured by ABL based on the information added to
APCB. coreboot does not need to configure these pads. This change
drops the RAM_ID configuration from trembyle baseboard. Dalboz never
really configured RAM_IDs in coreboot.

BUG=b:154351731

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ie1dfcc3c185304d917ab4386920445ba0119ac69
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2252710
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42720
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Furquan Shaikh 2020-06-18 12:45:15 -07:00
parent 39a6145e41
commit 624c1ca04e
1 changed files with 0 additions and 10 deletions
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10
src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
View File

@ -28,20 +28,10 @@ static const struct soc_amd_gpio gpio_set_stage_rom[] = {
PAD_GPO(GPIO_68, HIGH),
/* EN_PWR_CAMERA - reset */
PAD_GPO(GPIO_76, LOW),
/* RAM_ID_4 */
PAD_GPI(GPIO_84, PULL_NONE),
/* CLK_REQ0_L - WIFI */
PAD_NF(GPIO_92, CLK_REQ0_L, PULL_UP),
/* CLK_REQ1_L - SD Card */
PAD_NF(GPIO_115, CLK_REQ1_L, PULL_UP),
/* RAM_ID_3 */
PAD_GPI(GPIO_116, PULL_NONE),
/* RAM_ID_1 */
PAD_GPI(GPIO_120, PULL_NONE),
/* RAM_ID_0 */
PAD_GPI(GPIO_121, PULL_NONE),
/* RAM_ID_2 */
PAD_GPI(GPIO_131, PULL_NONE),
/* CLK_REQ4_L - SSD */
PAD_NF(GPIO_132, CLK_REQ4_L, PULL_UP),
/* BIOS_FLASH_WP_ODL */