diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
index b515170ad0..2b2c32d083 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
@@ -70,6 +70,7 @@ chip soc/intel/apollolake
 			register "SataPortsEnable[0]" = "1"
 			register "SataPortsEnable[1]" = "1"
 			register "DisableSataSalpSupport" = "1"
+			register "sata_speed" = "SATA_GEN2"
 		end
 		device pci 13.0 on	# - RP 2 - PCIe A 0
 			register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
index 92bba65047..15ca3f117d 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
@@ -70,6 +70,7 @@ chip soc/intel/apollolake
 			register "SataPortsEnable[0]" = "1"
 			register "SataPortsEnable[1]" = "1"
 			register "DisableSataSalpSupport" = "1"
+			register "sata_speed" = "SATA_GEN2"
 		end
 		device pci 13.0 on	# - RP 2 - PCIe A 0
 			register "pcie_rp_clkreq_pin[2]" = "0"
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
index 8223f68bab..3c907e3c78 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
@@ -41,6 +41,7 @@ chip soc/intel/apollolake
 			register "SataPortsEnable[0]" = "1"
 			register "SataPortsEnable[1]" = "1"
 			register "DisableSataSalpSupport" = "1"
+			register "sata_speed" = "SATA_GEN2"
 		end
 		device pci 13.0 on	# - RP 2 - PCIe A 0
 			register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"