From 6256fb63fff9db1e7f77f58da5c9514eb783c199 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Mon, 22 May 2023 14:45:42 +0200 Subject: [PATCH] mb/siemens/{mc_apl2,mc_apl5,mc_apl6}: Limit SATA speed to Gen 2 Due to mainboard restrictions a SATA link at Gen 3 can cause issues as the margin is not big enough. Limit SATA speed to Gen 2 to achieve a more robust SATA connection. Change-Id: Ifdea4542836b9c75b5507324fbb06b9566a6fe1d Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/75365 Reviewed-by: Jan Samek Tested-by: build bot (Jenkins) --- src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb | 1 + src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb | 1 + src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb | 1 + 3 files changed, 3 insertions(+) diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index b515170ad0..2b2c32d083 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -70,6 +70,7 @@ chip soc/intel/apollolake register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "DisableSataSalpSupport" = "1" + register "sata_speed" = "SATA_GEN2" end device pci 13.0 on # - RP 2 - PCIe A 0 register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb index 92bba65047..15ca3f117d 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb @@ -70,6 +70,7 @@ chip soc/intel/apollolake register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "DisableSataSalpSupport" = "1" + register "sata_speed" = "SATA_GEN2" end device pci 13.0 on # - RP 2 - PCIe A 0 register "pcie_rp_clkreq_pin[2]" = "0" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb index 8223f68bab..3c907e3c78 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb @@ -41,6 +41,7 @@ chip soc/intel/apollolake register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "DisableSataSalpSupport" = "1" + register "sata_speed" = "SATA_GEN2" end device pci 13.0 on # - RP 2 - PCIe A 0 register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"