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cpu/x86: Add definition for SMRR_PHYS_MASK_LOCK 

The IA32_SMRR_PHYS_MASK MSR contains a 'Lock' bit, which will cause the
core to generate a #GP if the SMRR_BASE or SMRR_MASK registers are
written to after the Lock bit is set; this is helpful with securing SMM.

BUG=b:164489598

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I784d1d1abec0a0fe0ee267118d084ac594a51647
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Tim Wawrzynczak 2020-09-01 16:08:02 -06:00 committed by Patrick Georgi
parent 7f844ab8b7
commit 62669a24ea
1 changed files with 1 additions and 0 deletions
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1
src/include/cpu/x86/mtrr.h
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@ -30,6 +30,7 @@
#define IA32_SMRR_PHYS_BASE 0x1f2
#define IA32_SMRR_PHYS_MASK 0x1f3
#define SMRR_PHYS_MASK_LOCK (1 << 10)
/* Specific to model_6fx and model_1067x */
#define MSR_SMRR_PHYS_BASE 0xa0