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soc/amd/cezanne/chip.h: add DPTC and tablet mode options 

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I39218b79a79f1ccaf1a58408c6bb5161acea64aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54073
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2021-05-12 01:17:35 +02:00
parent 7216053a42
commit 62682e79a7
1 changed files with 8 additions and 0 deletions
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src/soc/amd/cezanne/chip.h
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@ -75,6 +75,14 @@ struct soc_amd_cezanne_config {
uint32_t telemetry_vddcrsocfull_scale_current_mA; uint32_t telemetry_vddcrsocfull_scale_current_mA;
uint32_t telemetry_vddcrsocoffset; uint32_t telemetry_vddcrsocoffset;
/* Enable dptc for tablet mode (0 = disable, 1 = enable) */
uint8_t dptc_enable;
/* STAPM Configuration for tablet mode (need enable dptc_enable first) */
uint32_t fast_ppt_limit_tablet_mode_mW;
uint32_t slow_ppt_limit_tablet_mode_mW;
uint32_t sustained_power_limit_tablet_mode_mW;
uint32_t thermctl_limit_tablet_mode_degreeC;
}; };
#endif /* CEZANNE_CHIP_H */ #endif /* CEZANNE_CHIP_H */