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soc/intel/common/smbus: Don't clear random bits

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FSP might have done some settings for us there. Use pci_update_config32()
since the register is documented to be 32 bits wide.

Change-Id: I995e8a731a6958f10600174d031bb94f5a0a66db
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/21072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Nico Huber 2017-08-17 16:08:00 +02:00 committed by Nico Huber
parent 3f09b0ffef
commit 6278867065
1 changed files with 2 additions and 4 deletions
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6
src/soc/intel/common/block/smbus/smbus.c
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@ -53,12 +53,10 @@ static struct smbus_bus_operations lops_smbus_bus = {
static void pch_smbus_init(device_t dev) static void pch_smbus_init(device_t dev)
{ {
struct resource *res; struct resource *res;
u16 reg16;
/* Enable clock gating */ /* Enable clock gating */
reg16 = pci_read_config32(dev, 0x80); pci_update_config32(dev, 0x80,
reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14)); ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14)), 0);
pci_write_config32(dev, 0x80, reg16);
/* Set Receive Slave Address */ /* Set Receive Slave Address */
res = find_resource(dev, PCI_BASE_ADDRESS_4); res = find_resource(dev, PCI_BASE_ADDRESS_4);