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mb/gigabyte: Get rid of whitespace before tab 

Change-Id: I0b0a09098bd4185ae36f1468ebc151e39668ee86
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Elyes HAOUAS 2018-05-28 13:28:48 +02:00 committed by Patrick Georgi
parent b262293607
commit 6284c7e6de
9 changed files with 67 additions and 67 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
View File

@ -28,7 +28,7 @@ chip northbridge/intel/x4x # Northbridge
device pci 0.0 on # Host Bridge
subsystemid 0x1458 0x5000
end
device pci 2.0 on # Integrated graphics controller
device pci 2.0 on # Integrated graphics controller
subsystemid 0x1458 0xd000
end
device pci 2.1 on # Integrated graphics controller 2

2
src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb
View File

@ -81,7 +81,7 @@ chip northbridge/intel/sandybridge
irq 0x70 = 7
drq 0x74 = 4
end
device pnp 2e.4 on # Environment Controller
device pnp 2e.4 on # Environment Controller
io 0x60 = 0x0a30
irq 0x70 = 9
io 0x62 = 0x0a20

4
src/mainboard/gigabyte/ma785gm/devicetree.cb
View File

@ -10,7 +10,7 @@ chip northbridge/amd/amdfam10/root_complex
chip northbridge/amd/amdfam10
device pci 18.0 on # northbridge
chip southbridge/amd/rs780
device pci 0.0 on end # HT 0x9601
device pci 0.0 on end # HT 0x9601
device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
device pci 3.0 off end # PCIE P2P bridge 0x960b
@ -41,7 +41,7 @@ chip northbridge/amd/amdfam10/root_complex
device pci 13.0 on end # USB
device pci 13.1 on end # USB
device pci 13.2 on end # USB
device pci 14.0 on # SM
device pci 14.0 on # SM
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end

38
src/mainboard/gigabyte/ma785gm/dsdt.asl
View File

@ -239,9 +239,9 @@ DefinitionBlock (
PWMK, 1,
PWNS, 1,
/* Offset(0x61), */ /* Options_1 */
/* ,7, */
/* R617,1, */
/* Offset(0x61), */ /* Options_1 */
/* ,7, */
/* R617,1, */
Offset(0x65), /* UsbPMControl */
, 4,
@ -837,7 +837,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\_SB.SBRI, 0x13)) {
* Store(0,\_SB.PWDE)
* Store(0,\_SB.PWDE)
*}
*/
@ -853,13 +853,13 @@ DefinitionBlock (
* used, so it could be removed.
*
*
* \_GTS OEM Going To Sleep method
* \_GTS OEM Going To Sleep method
*
* Entry:
* Arg0=The value of the sleeping state S1=1, S2=2
* Entry:
* Arg0=The value of the sleeping state S1=1, S2=2
*
* Exit:
* -none-
* Exit:
* -none-
*
* Method(\_GTS, 1) {
* DBGO("\\_GTS\n")
@ -1026,7 +1026,7 @@ DefinitionBlock (
/* PCIe HotPlug event */
/* Method(_L0F) {
* DBGO("\\_GPE\\_L0F\n")
* DBGO("\\_GPE\\_L0F\n")
* }
*/
@ -1049,19 +1049,19 @@ DefinitionBlock (
/* GPM0 SCI event - Moved to USB.asl */
/* Method(_L13) {
* DBGO("\\_GPE\\_L13\n")
* DBGO("\\_GPE\\_L13\n")
* }
*/
/* GPM1 SCI event - Moved to USB.asl */
/* Method(_L14) {
* DBGO("\\_GPE\\_L14\n")
* DBGO("\\_GPE\\_L14\n")
* }
*/
/* GPM2 SCI event - Moved to USB.asl */
/* Method(_L15) {
* DBGO("\\_GPE\\_L15\n")
* DBGO("\\_GPE\\_L15\n")
* }
*/
@ -1073,7 +1073,7 @@ DefinitionBlock (
/* GPM8 SCI event - Moved to USB.asl */
/* Method(_L17) {
* DBGO("\\_GPE\\_L17\n")
* DBGO("\\_GPE\\_L17\n")
* }
*/
@ -1090,7 +1090,7 @@ DefinitionBlock (
/* GPM4 SCI event - Moved to USB.asl */
/* Method(_L19) {
* DBGO("\\_GPE\\_L19\n")
* DBGO("\\_GPE\\_L19\n")
* }
*/
@ -1121,7 +1121,7 @@ DefinitionBlock (
/* GPIO2 or GPIO66 SCI event */
/* Method(_L1E) {
* DBGO("\\_GPE\\_L1E\n")
* DBGO("\\_GPE\\_L1E\n")
* }
*/
@ -1131,7 +1131,7 @@ DefinitionBlock (
* }
*/
} /* End Scope GPE */
} /* End Scope GPE */
#include "acpi/usb.asl"
@ -1520,7 +1520,7 @@ DefinitionBlock (
)
Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
@ -1634,7 +1634,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\SBRI, 0x13)) {
* Store(0,\PWDE)
* Store(0,\PWDE)
* }
*/
} /* End Method(_SB._INI) */

4
src/mainboard/gigabyte/ma785gmt/devicetree.cb
View File

@ -10,7 +10,7 @@ chip northbridge/amd/amdfam10/root_complex
chip northbridge/amd/amdfam10
device pci 18.0 on # northbridge
chip southbridge/amd/rs780
device pci 0.0 on end # HT 0x9600
device pci 0.0 on end # HT 0x9600
device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
device pci 3.0 on end # PCIE P2P bridge 0x960b
@ -41,7 +41,7 @@ chip northbridge/amd/amdfam10/root_complex
device pci 13.0 on end # USB
device pci 13.1 on end # USB
device pci 13.2 on end # USB
device pci 14.0 on # SM
device pci 14.0 on # SM
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end

38
src/mainboard/gigabyte/ma785gmt/dsdt.asl
View File

@ -239,9 +239,9 @@ DefinitionBlock (
PWMK, 1,
PWNS, 1,
/* Offset(0x61), */ /* Options_1 */
/* ,7, */
/* R617,1, */
/* Offset(0x61), */ /* Options_1 */
/* ,7, */
/* R617,1, */
Offset(0x65), /* UsbPMControl */
, 4,
@ -837,7 +837,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\_SB.SBRI, 0x13)) {
* Store(0,\_SB.PWDE)
* Store(0,\_SB.PWDE)
*}
*/
@ -853,13 +853,13 @@ DefinitionBlock (
* used, so it could be removed.
*
*
* \_GTS OEM Going To Sleep method
* \_GTS OEM Going To Sleep method
*
* Entry:
* Arg0=The value of the sleeping state S1=1, S2=2
* Entry:
* Arg0=The value of the sleeping state S1=1, S2=2
*
* Exit:
* -none-
* Exit:
* -none-
*
* Method(\_GTS, 1) {
* DBGO("\\_GTS\n")
@ -1026,7 +1026,7 @@ DefinitionBlock (
/* PCIe HotPlug event */
/* Method(_L0F) {
* DBGO("\\_GPE\\_L0F\n")
* DBGO("\\_GPE\\_L0F\n")
* }
*/
@ -1049,19 +1049,19 @@ DefinitionBlock (
/* GPM0 SCI event - Moved to USB.asl */
/* Method(_L13) {
* DBGO("\\_GPE\\_L13\n")
* DBGO("\\_GPE\\_L13\n")
* }
*/
/* GPM1 SCI event - Moved to USB.asl */
/* Method(_L14) {
* DBGO("\\_GPE\\_L14\n")
* DBGO("\\_GPE\\_L14\n")
* }
*/
/* GPM2 SCI event - Moved to USB.asl */
/* Method(_L15) {
* DBGO("\\_GPE\\_L15\n")
* DBGO("\\_GPE\\_L15\n")
* }
*/
@ -1073,7 +1073,7 @@ DefinitionBlock (
/* GPM8 SCI event - Moved to USB.asl */
/* Method(_L17) {
* DBGO("\\_GPE\\_L17\n")
* DBGO("\\_GPE\\_L17\n")
* }
*/
@ -1090,7 +1090,7 @@ DefinitionBlock (
/* GPM4 SCI event - Moved to USB.asl */
/* Method(_L19) {
* DBGO("\\_GPE\\_L19\n")
* DBGO("\\_GPE\\_L19\n")
* }
*/
@ -1121,7 +1121,7 @@ DefinitionBlock (
/* GPIO2 or GPIO66 SCI event */
/* Method(_L1E) {
* DBGO("\\_GPE\\_L1E\n")
* DBGO("\\_GPE\\_L1E\n")
* }
*/
@ -1131,7 +1131,7 @@ DefinitionBlock (
* }
*/
} /* End Scope GPE */
} /* End Scope GPE */
#include "acpi/usb.asl"
@ -1520,7 +1520,7 @@ DefinitionBlock (
)
Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
@ -1634,7 +1634,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\SBRI, 0x13)) {
* Store(0,\PWDE)
* Store(0,\PWDE)
* }
*/
} /* End Method(_SB._INI) */

4
src/mainboard/gigabyte/ma785gmt/mainboard.c
View File

@ -150,7 +150,7 @@ static void set_gpio40_gfx(void)
dword = pci_read_config32(sm_dev, 0xfc);
dword &= ~(1 << 10);
/* When the gpio40 is configured as GPIO, this will represent the output value*/
/* When the gpio40 is configured as GPIO, this will represent the output value*/
/* 1 :enable two x8 , 0 : master slot enable only */
dword |= (1 << 26);
pci_write_config32(sm_dev, 0xfc, dword);
@ -162,7 +162,7 @@ static void set_gpio40_gfx(void)
dword = pci_read_config32(sm_dev, 0xfc);
dword &= ~(1 << 10);
/* When the gpio40 is configured as GPIO, this will represent the output value*/
/* When the gpio40 is configured as GPIO, this will represent the output value*/
/* 1 :enable two x8 , 0 : master slot enable only */
dword &= ~(1 << 26);
pci_write_config32(sm_dev, 0xfc, dword);

4
src/mainboard/gigabyte/ma78gm/devicetree.cb
View File

@ -10,7 +10,7 @@ chip northbridge/amd/amdfam10/root_complex
chip northbridge/amd/amdfam10
device pci 18.0 on # northbridge
chip southbridge/amd/rs780
device pci 0.0 on end # HT 0x9600
device pci 0.0 on end # HT 0x9600
device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
device pci 3.0 off end # PCIE P2P bridge 0x960b
@ -40,7 +40,7 @@ chip northbridge/amd/amdfam10/root_complex
device pci 13.0 on end # USB
device pci 13.1 on end # USB
device pci 13.2 on end # USB
device pci 14.0 on # SM
device pci 14.0 on # SM
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end

38
src/mainboard/gigabyte/ma78gm/dsdt.asl
View File

@ -239,9 +239,9 @@ DefinitionBlock (
PWMK, 1,
PWNS, 1,
/* Offset(0x61), */ /* Options_1 */
/* ,7, */
/* R617,1, */
/* Offset(0x61), */ /* Options_1 */
/* ,7, */
/* R617,1, */
Offset(0x65), /* UsbPMControl */
, 4,
@ -837,7 +837,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\_SB.SBRI, 0x13)) {
* Store(0,\_SB.PWDE)
* Store(0,\_SB.PWDE)
*}
*/
@ -853,13 +853,13 @@ DefinitionBlock (
* used, so it could be removed.
*
*
* \_GTS OEM Going To Sleep method
* \_GTS OEM Going To Sleep method
*
* Entry:
* Arg0=The value of the sleeping state S1=1, S2=2
* Entry:
* Arg0=The value of the sleeping state S1=1, S2=2
*
* Exit:
* -none-
* Exit:
* -none-
*
* Method(\_GTS, 1) {
* DBGO("\\_GTS\n")
@ -1026,7 +1026,7 @@ DefinitionBlock (
/* PCIe HotPlug event */
/* Method(_L0F) {
* DBGO("\\_GPE\\_L0F\n")
* DBGO("\\_GPE\\_L0F\n")
* }
*/
@ -1049,19 +1049,19 @@ DefinitionBlock (
/* GPM0 SCI event - Moved to USB.asl */
/* Method(_L13) {
* DBGO("\\_GPE\\_L13\n")
* DBGO("\\_GPE\\_L13\n")
* }
*/
/* GPM1 SCI event - Moved to USB.asl */
/* Method(_L14) {
* DBGO("\\_GPE\\_L14\n")
* DBGO("\\_GPE\\_L14\n")
* }
*/
/* GPM2 SCI event - Moved to USB.asl */
/* Method(_L15) {
* DBGO("\\_GPE\\_L15\n")
* DBGO("\\_GPE\\_L15\n")
* }
*/
@ -1073,7 +1073,7 @@ DefinitionBlock (
/* GPM8 SCI event - Moved to USB.asl */
/* Method(_L17) {
* DBGO("\\_GPE\\_L17\n")
* DBGO("\\_GPE\\_L17\n")
* }
*/
@ -1090,7 +1090,7 @@ DefinitionBlock (
/* GPM4 SCI event - Moved to USB.asl */
/* Method(_L19) {
* DBGO("\\_GPE\\_L19\n")
* DBGO("\\_GPE\\_L19\n")
* }
*/
@ -1121,7 +1121,7 @@ DefinitionBlock (
/* GPIO2 or GPIO66 SCI event */
/* Method(_L1E) {
* DBGO("\\_GPE\\_L1E\n")
* DBGO("\\_GPE\\_L1E\n")
* }
*/
@ -1131,7 +1131,7 @@ DefinitionBlock (
* }
*/
} /* End Scope GPE */
} /* End Scope GPE */
#include "acpi/usb.asl"
@ -1520,7 +1520,7 @@ DefinitionBlock (
)
Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
@ -1634,7 +1634,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\SBRI, 0x13)) {
* Store(0,\PWDE)
* Store(0,\PWDE)
* }
*/
} /* End Method(_SB._INI) */