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mb/google/brya: Move typeC AUX configuration to variant 

TypeC AUX configuration is variant specific. So move into variant level.

BUG=b:205235144
TEST=No typeC port 0 AUX in felwinter.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I02bfea462cf4c6359fd8d5cca4368786ee03bc8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Eric Lai 2021-11-15 12:24:12 +08:00 committed by Felix Held
parent a592bef03f
commit 6296ae0258
2 changed files with 2 additions and 2 deletions
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2
src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
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@ -1,7 +1,5 @@
chip soc/intel/alderlake
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
# GPE configuration
register "pmc_gpe0_dw0" = "GPP_A"
register "pmc_gpe0_dw1" = "GPP_E"

2
src/mainboard/google/brya/variants/brya0/overridetree.cb
View File

@ -43,6 +43,8 @@ chip soc/intel/alderlake
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
# FIVR configurations for brya are disabled since the board doesn't have V1p05 and Vnn
# bypass rails implemented.
register "ext_fivr_settings" = "{