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soc/intel/alderlake: Hook-up public Alder Lake microcode 

CPUIDs and Engineering Samples decoding based on DOC #618427.

Keep MICROCODE_BLOB_UNDISCLOSED for PCH-N SKUs as microcode
blobs are still missing.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ibb1337e5cbf5b82fdaceb7eb4661d708a32ff0ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65564
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
This commit is contained in:
Michał Żygowski 2022-06-30 16:22:35 +02:00 committed by Felix Held
parent 44c3759c22
commit 6297df85d6
2 changed files with 19 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/intel/alderlake/Kconfig
View File

@ -20,6 +20,7 @@ config SOC_INTEL_ALDERLAKE_PCH_M
config SOC_INTEL_ALDERLAKE_PCH_N
bool
select SOC_INTEL_ALDERLAKE
select MICROCODE_BLOB_UNDISCLOSED
help
Choose this option if your mainboard has a PCH-N chipset.
@ -73,7 +74,6 @@ config CPU_SPECIFIC_OPTIONS
select INTEL_TME
select MRC_SETTINGS_PROTECT
select PARALLEL_MP_AP_WORK
select MICROCODE_BLOB_UNDISCLOSED
select PLATFORM_USES_FSP2_2
select PMC_GLOBAL_RESET_ENABLE_LOCK
select SOC_INTEL_COMMON

18
src/soc/intel/alderlake/Makefile.inc
View File

@ -69,6 +69,24 @@ endif
CPPFLAGS_common += -I$(src)/soc/intel/alderlake
CPPFLAGS_common += -I$(src)/soc/intel/alderlake/include
ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_S),y)
# 06-97-00, 06-97-01, 06-97-04 are ADL-S Engineering Samples
# 06-97-02 are ADL-S/HX Quality Samples but also ADL-HX Engineering Samples
# ADL-S/HX C0
cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-97-02
# ADL-S H0
cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-97-05
else
ifneq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_N),y)
# 06-9a-00, 06-9a-01 are ADL-P/ADL-M Engineering Samples
# Missing 06-9a-02 ADL-P K0
# ADL-P L0
cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9a-03
# ADL-P R0 and ADL-M R0
cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9a-04
endif
endif
ifeq ($(CONFIG_STITCH_ME_BIN),y)
$(eval $(call cse_add_dummy_to_bp1_bp2,DLMP))