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Remove a couple of CONFIG_ prefixes that shouldn't have happened. 

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Patrick Georgi 2009-08-26 18:14:30 +00:00
parent bca3b92df2
commit 62b3513d63
5 changed files with 11 additions and 11 deletions
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4
src/drivers/i2c/adm1026/adm1026.c
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@ -17,7 +17,7 @@
#define CFG1_THERM_HOT 0x10
#define CFT1_DAC_AFC 0x20
#define CFG1_PWM_AFC 0x40
#define CFG1CONFIG_RESET 0x80
#define CFG1_RESET 0x80
#define ADM1026_REG_CONFIG2 0x01
#define ADM1026_REG_CONFIG3 0x07
@ -40,7 +40,7 @@ static void adm1026_enable_monitoring(device_t dev)
int result;
result = smbus_read_byte(dev, ADM1026_REG_CONFIG1);
result = (result | CFG1_MONITOR) & ~(CFG1_INT_CLEAR | CFG1CONFIG_RESET);
result = (result | CFG1_MONITOR) & ~(CFG1_INT_CLEAR | CFG1_RESET);
result = smbus_write_byte(dev, ADM1026_REG_CONFIG1, result);
result = smbus_read_byte(dev, ADM1026_REG_CONFIG1);

8
src/northbridge/amd/amdfam10/amdfam10_acpi.c
View File

@ -190,7 +190,7 @@ void update_ssdt(void *ssdt)
u8 *CBST;
u8 *CBBX;
u8 *CBS2;
u8 *CONFIG_CBB2;
u8 *CBB2;
int i;
@ -208,7 +208,7 @@ void update_ssdt(void *ssdt)
HCDN = ssdt+0x57a; //+5 will be next HCDN
CBBX = ssdt+0x61f; //
CBST = ssdt+0x626;
CONFIG_CBB2 = ssdt+0x62d; //
CBB2 = ssdt+0x62d; //
CBS2 = ssdt+0x634;
for(i=0;i<HC_NUMS;i++) {
@ -260,10 +260,10 @@ void update_ssdt(void *ssdt)
if((CONFIG_CBB == 0xff) && (sysconf.nodes>32)) {
*CBS2 = 0x0f;
*CONFIG_CBB2 = (u8)(CONFIG_CBB-1);
*CBB2 = (u8)(CONFIG_CBB-1);
} else {
*CBS2 = 0x00;
*CONFIG_CBB2 = 0x00;
*CBB2 = 0x00;
}
}

4
src/northbridge/ibm/cpc710/cpc710_pci.c
View File

@ -45,7 +45,7 @@ cpc710_pci_init(void)
setCPC710_PCI32(CPC710_PCIL0_MSIZE, CPC710_PCI32_MEM_SIZE);
setCPC710_PCI32(CPC710_PCIL0_IOSIZE, CPC710_PCI32_IO_SIZE);
setCPC710_PCI32(CPC710_PCIL0_SMBAR, CPC710_PCI32_MEM_BASE);
setCPC710_PCI32(CPC710_PCIL0_SIBAR, CPC710_PCI32CONFIG_IO_BASE);
setCPC710_PCI32(CPC710_PCIL0_SIBAR, CPC710_PCI32_IO_BASE);
setCPC710_PCI32(CPC710_PCIL0_CTLRW, 0x00000000);
setCPC710_PCI32(CPC710_PCIL0_PSSIZE, 0x00000080);
setCPC710_PCI32(CPC710_PCIL0_BARPS, 0x00000000);
@ -94,7 +94,7 @@ cpc710_pci_init(void)
setCPC710_PCI64(CPC710_PCIL0_MSIZE, CPC710_PCI64_MEM_SIZE);
setCPC710_PCI64(CPC710_PCIL0_IOSIZE, CPC710_PCI64_IO_SIZE);
setCPC710_PCI64(CPC710_PCIL0_SMBAR, CPC710_PCI64_MEM_BASE);
setCPC710_PCI64(CPC710_PCIL0_SIBAR, CPC710_PCI64CONFIG_IO_BASE);
setCPC710_PCI64(CPC710_PCIL0_SIBAR, CPC710_PCI64_IO_BASE);
setCPC710_PCI64(CPC710_PCIL0_CTLRW, 0x02000000);
setCPC710_PCI64(CPC710_PCIL0_PSSIZE, 0x00000080);

4
src/northbridge/ibm/cpc710/cpc710_pci.h
View File

@ -28,13 +28,13 @@
#define CPC710_PCI32_MEM_SIZE 0xf8000000
#define CPC710_PCI32_MEM_BASE 0xc0000000
#define CPC710_PCI32_IO_SIZE 0xf8000000
#define CPC710_PCI32CONFIG_IO_BASE 0x80000000
#define CPC710_PCI32_IO_BASE 0x80000000
//#define CPC710_PCI64_CONFIG 0xff400000
//#define CPC710_PCI64_MEM_SIZE 0xf8000000
//#define CPC710_PCI64_MEM_BASE 0xc8000000
//#define CPC710_PCI64_IO_SIZE 0xf8000000
//#define CPC710_PCI64CONFIG_IO_BASE 0x88000000
//#define CPC710_PCI64_IO_BASE 0x88000000
#define CPC710_PCIL0_PSEA 0xf6110
#define CPC710_PCIL0_PCIDG 0xf6120

2
src/southbridge/amd/sb600/sb600_early_setup.c
View File

@ -430,7 +430,7 @@ static void sb600_devices_por_init(void)
/*CIM set this register; but I didn't find its description in RPR.
On DBM690T platform, I didn't find different between set and skip this register.
But on Filbert platform, the CONFIG_DEBUG message from serial port on Peanut board can't be displayed
But on Filbert platform, the DEBUG message from serial port on Peanut board can't be displayed
after the bit0 of this register is set.
pci_write_config8(dev, 0x04, 0x21);
*/