mb/lenovo/*: Add support for VBOOT on 8MiB devices

Enable VBOOT support on all devices that have a 8 MiB flash, using a
single RW_MAIN_A partition, allowing the use of tianocore payload in
both RW_MAIN_A and WP_RO.

* Add VBNV section to cmos.layout
* Add FMAP for VBOOT and regular boot
* Select Kconfigs for VBOOT
* Enable VBOOT_SLOTS_RW_A by default

Also build test VBOOT on Lenovo T420.

Tested on Lenovo T520 using Icb7b263ed86551cc53e1db7babccaca6b3ae2fe6.

Change-Id: Icb7b263ed86551cc53e1db7babccaca6b3ae2fe6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Patrick Rudolph 2019-05-04 14:19:32 +02:00 committed by Patrick Georgi
parent 2521211753
commit 62bc1cb88b
17 changed files with 273 additions and 0 deletions

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@ -4,4 +4,6 @@ CONFIG_VENDOR_LENOVO=y
CONFIG_BOARD_LENOVO_T420=y
CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES=y
CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS=y
CONFIG_VBOOT=y
CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW=y
# CONFIG_INTEL_CHIPSET_LOCKDOWN is not set

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@ -28,6 +28,26 @@ config BOARD_SPECIFIC_OPTIONS
# Workaround for EC/KBC IRQ1.
select SERIRQ_CONTINUOUS_MODE
config VBOOT
select VBOOT_VBNV_CMOS
select GBB_FLAG_DISABLE_LID_SHUTDOWN
select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
select GBB_FLAG_DISABLE_FWMP
select HAS_RECOVERY_MRC_CACHE
config VBOOT_SLOTS_RW_A
default y
config VBOOT_VBNV_OFFSET
hex
default 0x2a
config FMDFILE
string
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd"
config MAINBOARD_DIR
string
default lenovo/t420

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@ -0,0 +1,16 @@
FLASH@0xff800000 0x800000 {
SI_ALL@0x0 0x500000 {
SI_DESC@0x0 0x1000
SI_GBE@0x1000 0x2000
SI_ME@0x3000 0x4ed000
}
SI_BIOS@0x500000 0x300000 {
RW_MRC_CACHE@0 0x10000
SMMSTORE(PRESERVE)@0x10000 0x40000
WP_RO@0x50000 0x2a0000 {
FMAP@0x0 0x800
COREBOOT(CBFS)@0x1000 0x29f000
}
}
}

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@ -81,6 +81,9 @@ entries
440 8 h 0 volume
# VBOOT
448 128 r 0 vbnv
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3

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@ -0,0 +1,29 @@
FLASH@0xff800000 0x800000 {
SI_ALL@0x0 0x500000 {
SI_DESC@0x0 0x1000
SI_GBE@0x1000 0x2000
SI_ME@0x3000 0x4ed000
}
SI_BIOS@0x500000 0x300000 {
RW_SECTION_A@0x00000 0x180000 {
VBLOCK_A@0x0 0x10000
FW_MAIN_A(CBFS)@0x10000 0x16ffc0
RW_FWID_A@0x17ffc0 0x40
}
UNIFIED_MRC_CACHE@0x180000 0x20000 {
RECOVERY_MRC_CACHE@0x0 0x10000
RW_MRC_CACHE@0x10000 0x10000
}
RW_VPD(PRESERVE)@0x1a0000 0x1000
SMMSTORE(PRESERVE)@0x1a1000 0x40000
WP_RO@0x1e1000 0x11f000 {
FMAP@0x0 0x800
RO_FRID@0x800 0x40
RO_PADDING@0x840 0x7c0
RO_VPD(PRESERVE)@0x1000 0x1000
GBB@0x2000 0x1e000
COREBOOT(CBFS)@0x20000 0xff000
}
}
}

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@ -27,6 +27,26 @@ config BOARD_SPECIFIC_OPTIONS
# Workaround for EC/KBC IRQ1.
select SERIRQ_CONTINUOUS_MODE
config VBOOT
select VBOOT_VBNV_CMOS
select GBB_FLAG_DISABLE_LID_SHUTDOWN
select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
select GBB_FLAG_DISABLE_FWMP
select HAS_RECOVERY_MRC_CACHE
config VBOOT_SLOTS_RW_A
default y
config VBOOT_VBNV_OFFSET
hex
default 0x2a
config FMDFILE
string
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd"
config MAINBOARD_DIR
string
default lenovo/t420s

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@ -0,0 +1,16 @@
FLASH@0xff800000 0x800000 {
SI_ALL@0x0 0x500000 {
SI_DESC@0x0 0x1000
SI_GBE@0x1000 0x2000
SI_ME@0x3000 0x4ed000
}
SI_BIOS@0x500000 0x300000 {
RW_MRC_CACHE@0 0x10000
SMMSTORE(PRESERVE)@0x10000 0x40000
WP_RO@0x50000 0x2a0000 {
FMAP@0x0 0x800
COREBOOT(CBFS)@0x1000 0x29f000
}
}
}

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@ -81,6 +81,9 @@ entries
440 8 h 0 volume
# VBOOT
448 128 r 0 vbnv
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3

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@ -0,0 +1,29 @@
FLASH@0xff800000 0x800000 {
SI_ALL@0x0 0x500000 {
SI_DESC@0x0 0x1000
SI_GBE@0x1000 0x2000
SI_ME@0x3000 0x4ed000
}
SI_BIOS@0x500000 0x300000 {
RW_SECTION_A@0x00000 0x180000 {
VBLOCK_A@0x0 0x10000
FW_MAIN_A(CBFS)@0x10000 0x16ffc0
RW_FWID_A@0x17ffc0 0x40
}
UNIFIED_MRC_CACHE@0x180000 0x20000 {
RECOVERY_MRC_CACHE@0x0 0x10000
RW_MRC_CACHE@0x10000 0x10000
}
RW_VPD(PRESERVE)@0x1a0000 0x1000
SMMSTORE(PRESERVE)@0x1a1000 0x40000
WP_RO@0x1e1000 0x11f000 {
FMAP@0x0 0x800
RO_FRID@0x800 0x40
RO_PADDING@0x840 0x7c0
RO_VPD(PRESERVE)@0x1000 0x1000
GBB@0x2000 0x1e000
COREBOOT(CBFS)@0x20000 0xff000
}
}
}

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@ -27,6 +27,21 @@ config BOARD_LENOVO_BASEBOARD_T520
if BOARD_LENOVO_BASEBOARD_T520
config VBOOT
select VBOOT_VBNV_CMOS
select GBB_FLAG_DISABLE_LID_SHUTDOWN
select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
select GBB_FLAG_DISABLE_FWMP
select HAS_RECOVERY_MRC_CACHE
config VBOOT_SLOTS_RW_A
default y
config VBOOT_VBNV_OFFSET
hex
default 0x2a
config VARIANT_DIR
string
default "t520" if BOARD_LENOVO_T520
@ -40,6 +55,11 @@ config DEVICETREE
string
default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
config FMDFILE
string
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd"
config MAINBOARD_PART_NUMBER
string
default "ThinkPad T520" if BOARD_LENOVO_T520

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@ -0,0 +1,16 @@
FLASH@0xff800000 0x800000 {
SI_ALL@0x0 0x500000 {
SI_DESC@0x0 0x1000
SI_GBE@0x1000 0x2000
SI_ME@0x3000 0x4ed000
}
SI_BIOS@0x500000 0x300000 {
RW_MRC_CACHE@0 0x10000
SMMSTORE(PRESERVE)@0x10000 0x40000
WP_RO@0x50000 0x2a0000 {
FMAP@0x0 0x800
COREBOOT(CBFS)@0x1000 0x29f000
}
}
}

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@ -81,6 +81,9 @@ entries
#437 3 r 0 unused
440 8 h 0 volume
# VBOOT
448 128 r 0 vbnv
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3

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@ -0,0 +1,29 @@
FLASH@0xff800000 0x800000 {
SI_ALL@0x0 0x500000 {
SI_DESC@0x0 0x1000
SI_GBE@0x1000 0x2000
SI_ME@0x3000 0x4ed000
}
SI_BIOS@0x500000 0x300000 {
RW_SECTION_A@0x00000 0x180000 {
VBLOCK_A@0x0 0x10000
FW_MAIN_A(CBFS)@0x10000 0x16ffc0
RW_FWID_A@0x17ffc0 0x40
}
UNIFIED_MRC_CACHE@0x180000 0x20000 {
RECOVERY_MRC_CACHE@0x0 0x10000
RW_MRC_CACHE@0x10000 0x10000
}
RW_VPD(PRESERVE)@0x1a0000 0x1000
SMMSTORE(PRESERVE)@0x1a1000 0x40000
WP_RO@0x1e1000 0x11f000 {
FMAP@0x0 0x800
RO_FRID@0x800 0x40
RO_PADDING@0x840 0x7c0
RO_VPD(PRESERVE)@0x1000 0x1000
GBB@0x2000 0x1e000
COREBOOT(CBFS)@0x20000 0xff000
}
}
}

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@ -26,6 +26,21 @@ config BOARD_SPECIFIC_OPTIONS
# Workaround for EC/KBC IRQ1.
select SERIRQ_CONTINUOUS_MODE
config VBOOT
select VBOOT_VBNV_CMOS
select GBB_FLAG_DISABLE_LID_SHUTDOWN
select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
select GBB_FLAG_DISABLE_FWMP
select HAS_RECOVERY_MRC_CACHE
config VBOOT_SLOTS_RW_A
default y
config VBOOT_VBNV_OFFSET
hex
default 0x2a
config MAINBOARD_DIR
string
default lenovo/x220
@ -35,6 +50,10 @@ config VARIANT_DIR
default "x220" if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I
default "x1" if BOARD_LENOVO_X1
config FMDFILE
string
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd"
config MAINBOARD_PART_NUMBER
string

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@ -0,0 +1,16 @@
FLASH@0xff800000 0x800000 {
SI_ALL@0x0 0x500000 {
SI_DESC@0x0 0x1000
SI_GBE@0x1000 0x2000
SI_ME@0x3000 0x4ed000
}
SI_BIOS@0x500000 0x300000 {
RW_MRC_CACHE@0 0x10000
SMMSTORE(PRESERVE)@0x10000 0x40000
WP_RO@0x50000 0x2a0000 {
FMAP@0x0 0x800
COREBOOT(CBFS)@0x1000 0x29f000
}
}
}

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@ -80,6 +80,9 @@ entries
#435 549 r 0 unused
440 8 h 0 volume
# VBOOT
448 128 r 0 vbnv
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3

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@ -0,0 +1,29 @@
FLASH@0xff800000 0x800000 {
SI_ALL@0x0 0x500000 {
SI_DESC@0x0 0x1000
SI_GBE@0x1000 0x2000
SI_ME@0x3000 0x4ed000
}
SI_BIOS@0x500000 0x300000 {
RW_SECTION_A@0x00000 0x180000 {
VBLOCK_A@0x0 0x10000
FW_MAIN_A(CBFS)@0x10000 0x16ffc0
RW_FWID_A@0x17ffc0 0x40
}
UNIFIED_MRC_CACHE@0x180000 0x20000 {
RECOVERY_MRC_CACHE@0x0 0x10000
RW_MRC_CACHE@0x10000 0x10000
}
RW_VPD(PRESERVE)@0x1a0000 0x1000
SMMSTORE(PRESERVE)@0x1a1000 0x40000
WP_RO@0x1e1000 0x11f000 {
FMAP@0x0 0x800
RO_FRID@0x800 0x40
RO_PADDING@0x840 0x7c0
RO_VPD(PRESERVE)@0x1000 0x1000
GBB@0x2000 0x1e000
COREBOOT(CBFS)@0x20000 0xff000
}
}
}