superio/smsc: Add support for the SCH555x series
Used by the OptiPlex 3020/7020/9020: - EMI and Runtime registers work - UART1 works (including IRQs) - PS/2 keyboard and mouse untested Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Change-Id: I9323198f1139cd0c3dd37f977ae7693b721654f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
This commit is contained in:
Mate Kukri
Felix Held
parent
b9523a4281
commit
62c25351c1
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@ -13,3 +13,4 @@ subdirs-y += mec1308
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subdirs-y += smscsuperio
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subdirs-y += smscsuperio
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subdirs-y += sio1036
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subdirs-y += sio1036
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subdirs-y += sch5545
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subdirs-y += sch5545
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subdirs-y += sch555x
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@ -0,0 +1,4 @@
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## SPDX-License-Identifier: GPL-2.0-only
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config SUPERIO_SMSC_SCH555x
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bool
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@ -0,0 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0-only
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bootblock-$(CONFIG_SUPERIO_SMSC_SCH555x) += emi.c bootblock.c
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ramstage-$(CONFIG_SUPERIO_SMSC_SCH555x) += ramstage.c
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@ -0,0 +1,70 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/io.h>
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#include <device/pnp_ops.h>
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#include "sch555x.h"
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static void pnp_enter_conf_state(pnp_devfn_t dev)
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{
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unsigned int port = dev >> 8;
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outb(0x55, port);
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}
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static void pnp_exit_conf_state(pnp_devfn_t dev)
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{
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unsigned int port = dev >> 8;
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outb(0xaa, port);
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}
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static void pnp_write_config32(pnp_devfn_t dev, uint8_t offset, uint32_t value)
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{
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pnp_write_config(dev, offset, value & 0xff);
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pnp_write_config(dev, offset + 1, (value >> 8) & 0xff);
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pnp_write_config(dev, offset + 2, (value >> 16) & 0xff);
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pnp_write_config(dev, offset + 3, (value >> 24) & 0xff);
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}
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/*
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* Do just enough init so that the motherboard specific magic EMI
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* sequences can be sent before sch555x_enable_serial is called
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*/
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void sch555x_early_init(pnp_devfn_t global_dev)
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{
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pnp_enter_conf_state(global_dev);
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// Enable IRQs
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pnp_set_logical_device(global_dev);
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pnp_write_config(global_dev, SCH555x_DEVICE_MODE, 0x04);
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// Map EMI and runtime registers
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pnp_devfn_t lpci_dev = PNP_DEV(global_dev >> 8, SCH555x_LDN_LPCI);
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pnp_set_logical_device(lpci_dev);
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pnp_write_config32(lpci_dev, SCH555x_LPCI_EMI_BAR,
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(SCH555x_EMI_IOBASE << 16) | 0x800f);
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pnp_write_config32(lpci_dev, SCH555x_LPCI_RUNTIME_BAR,
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(SCH555x_RUNTIME_IOBASE << 16) | 0x8a3f);
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pnp_exit_conf_state(global_dev);
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}
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void sch555x_enable_serial(pnp_devfn_t uart_dev, uint16_t serial_iobase)
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{
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pnp_enter_conf_state(uart_dev);
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// Set LPCI BAR register to map UART into I/O space
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pnp_devfn_t lpci_dev = PNP_DEV(uart_dev >> 8, SCH555x_LDN_LPCI);
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pnp_set_logical_device(lpci_dev);
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u8 uart_bar = (uart_dev & 0xff) == SCH555x_LDN_UART1
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? SCH555x_LPCI_UART1_BAR
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: SCH555x_LPCI_UART2_BAR;
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pnp_write_config32(lpci_dev, uart_bar, serial_iobase << 16 | 0x8707);
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// Set up the UART's configuration registers
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pnp_set_logical_device(uart_dev);
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pnp_set_enable(uart_dev, 1); // Activate
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pnp_write_config(uart_dev, 0x0f, 0x02); // Config select
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pnp_exit_conf_state(uart_dev);
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}
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@ -0,0 +1,41 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/io.h>
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#include <device/pnp_ops.h>
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#include "sch555x.h"
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uint8_t sch555x_emi_read8(uint16_t addr)
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{
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outw(addr | 0x8000, SCH555x_EMI_IOBASE + 2);
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return inb(SCH555x_EMI_IOBASE + 4);
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}
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uint16_t sch555x_emi_read16(uint16_t addr)
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{
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outw(addr | 0x8001, SCH555x_EMI_IOBASE + 2);
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return inw(SCH555x_EMI_IOBASE + 4);
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}
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uint32_t sch555x_emi_read32(uint16_t addr)
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{
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outw(addr | 0x8002, SCH555x_EMI_IOBASE + 2);
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return inl(SCH555x_EMI_IOBASE + 4);
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}
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void sch555x_emi_write8(uint16_t addr, uint8_t val)
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{
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outw(addr | 0x8000, SCH555x_EMI_IOBASE + 2);
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outb(val, SCH555x_EMI_IOBASE + 4);
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}
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void sch555x_emi_write16(uint16_t addr, uint16_t val)
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{
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outw(addr | 0x8001, SCH555x_EMI_IOBASE + 2);
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outw(val, SCH555x_EMI_IOBASE + 4);
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}
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void sch555x_emi_write32(uint16_t addr, uint32_t val)
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{
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outw(addr | 0x8002, SCH555x_EMI_IOBASE + 2);
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outl(val, SCH555x_EMI_IOBASE + 4);
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}
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@ -0,0 +1,141 @@
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;;/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/pnp.h>
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#include <pc80/keyboard.h>
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#include <superio/conf_mode.h>
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#include "sch555x.h"
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static void sch555x_init(struct device *dev)
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{
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if (dev->enabled && dev->path.pnp.device == SCH555x_LDN_8042)
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pc_keyboard_init(NO_AUX_DEVICE);
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}
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static uint8_t sch555x_ldn_to_bar(uint8_t ldn)
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{
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switch (ldn) {
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case SCH555x_LDN_LPCI:
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return SCH555x_LPCI_LPCI_BAR;
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case SCH555x_LDN_EMI:
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return SCH555x_LPCI_EMI_BAR;
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case SCH555x_LDN_UART1:
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return SCH555x_LPCI_UART1_BAR;
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case SCH555x_LDN_UART2:
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return SCH555x_LPCI_UART2_BAR;
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case SCH555x_LDN_RUNTIME:
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return SCH555x_LPCI_RUNTIME_BAR;
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case SCH555x_LDN_8042:
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return SCH555x_LPCI_8042_BAR;
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case SCH555x_LDN_FDC:
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return SCH555x_LPCI_FDC_BAR;
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case SCH555x_LDN_PP:
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return SCH555x_LPCI_PP_BAR;
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default:
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return 0;
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}
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}
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/*
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* IO BARs don't live in normal LDN configuration space but in the LPC interface.
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* Thus we ignore the index and choose what BAR to set just based on the LDN.
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*/
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static void sch555x_set_iobase(struct device *lpci, struct device *dev,
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uint8_t index, uint16_t iobase)
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{
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const uint8_t bar = sch555x_ldn_to_bar(dev->path.pnp.device);
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if (bar) {
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pnp_set_logical_device(lpci);
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pnp_unset_and_set_config(lpci, bar + 1, 0, 1 << 7);
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pnp_write_config(lpci, bar + 2, iobase & 0xff);
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pnp_write_config(lpci, bar + 3, (iobase >> 8) & 0xff);
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}
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}
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/*
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* IRQs don't live in normal LDN configuration space but in the LPC interface.
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*
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* The following fake offsets are used:
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* 0x70 => First IRQ
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* 0x72 => Second IRQ
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*/
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static void sch555x_set_irq(struct device *lpci, struct device *dev,
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uint8_t index, uint8_t irq)
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{
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if (index >= PNP_IDX_MSC0) {
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pnp_set_logical_device(dev);
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pnp_write_config(dev, index, irq);
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return;
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}
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pnp_set_logical_device(lpci);
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switch (index) {
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case 0x70:
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pnp_write_config(lpci, SCH555x_LPCI_IRQ(irq), dev->path.pnp.device);
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break;
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case 0x72:
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pnp_write_config(lpci, SCH555x_LPCI_IRQ(irq), dev->path.pnp.device | 0x80);
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break;
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}
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}
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/*
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* DMA channels don't live in normal LDN configuration space but in the LPC interface.
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*/
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static void sch555x_set_drq(struct device *lpci, struct device *dev,
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uint8_t index, uint8_t drq)
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{
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pnp_set_logical_device(lpci);
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pnp_write_config(lpci, SCH555x_LPCI_DMA(drq), dev->path.pnp.device | 0x80);
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}
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static void sch555x_set_resources(struct device *dev)
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{
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struct device *lpci = dev_find_slot_pnp(dev->path.pnp.port, SCH555x_LDN_LPCI);
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if (!lpci) {
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printk(BIOS_ERR, "SCH555x LPC interface not present in device tree!\n");
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return;
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}
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pnp_enter_conf_mode(dev);
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for (struct resource *res = dev->resource_list; res; res = res->next) {
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if (res->flags & IORESOURCE_IO)
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sch555x_set_iobase(lpci, dev, res->index, res->base);
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else if (res->flags & IORESOURCE_DRQ)
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sch555x_set_drq(lpci, dev, res->index, res->base);
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else if (res->flags & IORESOURCE_IRQ)
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sch555x_set_irq(lpci, dev, res->index, res->base);
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}
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pnp_exit_conf_mode(dev);
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}
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static void sch555x_enable_dev(struct device *dev)
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{
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static struct device_operations ops = {
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.read_resources = pnp_read_resources,
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.set_resources = sch555x_set_resources,
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.enable_resources = pnp_enable_resources,
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.enable = pnp_alt_enable,
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.init = sch555x_init,
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.ops_pnp_mode = &pnp_conf_mode_55_aa,
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};
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static struct pnp_info pnp_dev_info[] = {
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{ NULL, SCH555x_LDN_EMI, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, 0x0ff0 },
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{ NULL, SCH555x_LDN_8042, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, 0x0fff },
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{ NULL, SCH555x_LDN_UART1, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8 },
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{ NULL, SCH555x_LDN_UART2, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8 },
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{ NULL, SCH555x_LDN_LPCI, PNP_IO0, 0x0ffe },
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{ NULL, SCH555x_LDN_RUNTIME, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, 0x0fc0 },
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{ NULL, SCH555x_LDN_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ff8, },
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{ NULL, SCH555x_LDN_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ff8 },
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};
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pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
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}
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struct chip_operations superio_smsc_sch555x_ops = {
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CHIP_NAME("SMSC SCH555x Super I/O")
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.enable_dev = sch555x_enable_dev,
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};
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@ -0,0 +1,68 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef SUPERIO_SCH555x_H
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#define SUPERIO_SCH555x_H
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#include <types.h>
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// Global registers
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#define SCH555x_DEVICE_ID 0x20
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#define SCH555x_DEVICE_REV 0x21
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#define SCH555x_DEVICE_MODE 0x24
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// Logical device numbers
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#define SCH555x_LDN_EMI 0x00
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#define SCH555x_LDN_8042 0x01
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#define SCH555x_LDN_UART1 0x07
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#define SCH555x_LDN_UART2 0x08
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#define SCH555x_LDN_RUNTIME 0x0a
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#define SCH555x_LDN_FDC 0x0b
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#define SCH555x_LDN_LPCI 0x0c
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#define SCH555x_LDN_PP 0x11
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#define SCH555x_LDN_GLOBAL 0x3f
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// LPC interface registers
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#define SCH555x_LPCI_IRQ(i) (0x40 + (i))
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// DMA channel register is 2 bytes, we care about the second byte
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#define SCH555x_LPCI_DMA(i) (0x50 + (i) * 2 + 1)
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// BAR offset (inside LPCI) for each LDN
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#define SCH555x_LPCI_LPCI_BAR 0x60
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#define SCH555x_LPCI_EMI_BAR 0x64
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#define SCH555x_LPCI_UART1_BAR 0x68
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#define SCH555x_LPCI_UART2_BAR 0x6c
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#define SCH555x_LPCI_RUNTIME_BAR 0x70
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#define SCH555x_LPCI_8042_BAR 0x78
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#define SCH555x_LPCI_FDC_BAR 0x7c
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#define SCH555x_LPCI_PP_BAR 0x80
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// Runtime registers (in I/O space)
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#define SCH555x_RUNTIME_PME_STS 0x00
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#define SCH555x_RUNTIME_PME_EN 0x01
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#define SCH555x_RUNTIME_PME_EN1 0x05
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#define SCH555x_RUNTIME_LED 0x25
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// NOTE: not in the SCH5627P datasheet but Dell's firmware writes to it
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#define SCH555x_RUNTIME_UNK1 0x35
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// Needed in the bootblock, thus we map them at a fixed address
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#define SCH555x_EMI_IOBASE 0xa00
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#define SCH555x_RUNTIME_IOBASE 0xa40
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/*
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* EMI access
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*/
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uint8_t sch555x_emi_read8(uint16_t addr);
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uint16_t sch555x_emi_read16(uint16_t addr);
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uint32_t sch555x_emi_read32(uint16_t addr);
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void sch555x_emi_write8(uint16_t addr, uint8_t val);
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void sch555x_emi_write16(uint16_t addr, uint16_t val);
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void sch555x_emi_write32(uint16_t addr, uint32_t val);
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|
/*
|
||||||
|
* Bootblock entry points
|
||||||
|
*/
|
||||||
|
|
||||||
|
void sch555x_early_init(pnp_devfn_t global_dev);
|
||||||
|
void sch555x_enable_serial(pnp_devfn_t uart_dev, uint16_t serial_iobase);
|
||||||
|
|
||||||
|
#endif
|
||||||
Loading…
Reference in New Issue