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This patch implements support for the Intel 3100 integrated SuperIO and UART. 

Signed-off-by: Ed Swierk <eswierk@arastra.com>                                                                                                                                               
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>                                                                                                                                                   
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3156 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ed Swierk 2008-03-16 23:31:04 +00:00 committed by Stefan Reinauer
parent 791265a367
commit 62eee3ff4f
5 changed files with 246 additions and 0 deletions
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23
src/superio/intel/i3100/Config.lb Normal file
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##
## This file is part of the coreboot project.
##
## Copyright (C) 2008 Arastra, Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
config chip.h
object superio.o

33
src/superio/intel/i3100/chip.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Arastra, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef SUPERIO_INTEL_I3100_CHIP_H
#define SUPERIO_INTEL_I3100_CHIP_H
#include <device/device.h>
#include <uart8250.h>
extern struct chip_operations superio_intel_i3100_ops;
struct superio_intel_i3100_config {
struct uart8250 com1, com2;
};
#endif

30
src/superio/intel/i3100/i3100.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Arastra, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* Datasheet: http://www.intel.com/design/intarch/datashts/313458.htm */
#ifndef SUPERIO_INTEL_I3100_I3100_H
#define SUPERIO_INTEL_I3100_I3100_H
#define I3100_SP1 0x04 /* Com1 */
#define I3100_SP2 0x05 /* Com2 */
#define I3100_WDT 0x06 /* Watchdog timer */
#endif

52
src/superio/intel/i3100/i3100_early_serial.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Arastra, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/romcc_io.h>
#include "i3100.h"
static void i3100_sio_write(u8 port, u8 ldn, u8 index,
u8 value)
{
outb(0x07, port);
outb(ldn, port + 1);
outb(index, port);
outb(value, port + 1);
}
static void i3100_enable_serial(u8 port, u8 ldn, u16 iobase)
{
/* Enter configuration state */
outb(0x80, port);
outb(0x86, port);
/* Enable serial port */
i3100_sio_write(port, ldn, 0x30, 0x01);
/* Set serial port IO region */
i3100_sio_write(port, ldn, 0x60, (iobase >> 8) & 0xff);
i3100_sio_write(port, ldn, 0x61, iobase & 0xff);
/* Enable device interrupts, set UART_CLK predivide to 26 */
i3100_sio_write(port, 0x00, 0x29, 0x0b);
/* Exit configuration state */
outb(0x68, port);
outb(0x08, port);
}

108
src/superio/intel/i3100/superio.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Arastra, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdlib.h>
#include <device/device.h>
#include <device/pnp.h>
#include <uart8250.h>
#include "chip.h"
#include "i3100.h"
#include <arch/io.h>
static void pnp_enter_ext_func_mode(device_t dev)
{
outb(0x80, dev->path.u.pnp.port);
outb(0x86, dev->path.u.pnp.port);
}
static void pnp_exit_ext_func_mode(device_t dev)
{
outb(0x68, dev->path.u.pnp.port);
outb(0x08, dev->path.u.pnp.port);
}
static void i3100_init(device_t dev)
{
struct superio_intel_i3100_config *conf;
struct resource *res0;
if (!dev->enabled) {
return;
}
conf = dev->chip_info;
switch (dev->path.u.pnp.device) {
case I3100_SP1:
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com1);
break;
case I3100_SP2:
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com2);
break;
}
}
static void i3100_pnp_set_resources(device_t dev)
{
pnp_enter_ext_func_mode(dev);
pnp_set_resources(dev);
pnp_exit_ext_func_mode(dev);
}
static void i3100_pnp_enable_resources(device_t dev)
{
pnp_enter_ext_func_mode(dev);
pnp_enable_resources(dev);
pnp_exit_ext_func_mode(dev);
}
static void i3100_pnp_enable(device_t dev)
{
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(dev);
pnp_set_enable(dev, dev->enabled);
pnp_exit_ext_func_mode(dev);
}
static struct device_operations ops = {
.read_resources = pnp_read_resources,
.set_resources = i3100_pnp_set_resources,
.enable_resources = i3100_pnp_enable_resources,
.enable = i3100_pnp_enable,
.init = i3100_init,
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, I3100_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, I3100_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
};
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_intel_i3100_ops = {
CHIP_NAME("Intel 3100 Super I/O")
.enable_dev = enable_dev,
};