amd/amdfam10: Add runtime ACPI _PSS generation
Skeleton and ACPI generator interface taken from model_fxx powernow_acpi.c Small portions of FIDVID MSR code taken from model_10xxx fidvid.c Nearly completely rewritten for the P-state-based K10 CPU TEST: KFSN4-DRE with dual Opteron 8356 CPUs Verified CPU per-core dynamic state change with system load Verified reported P-state count and frequencies Stress-tested each CPU (all cores simultaneously) to verify proper P0 transition and configuration. Change-Id: Icf620ec96a3f163b62d96b5988184996641dd439 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8284 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Timothy Pearson
Alexandru Gagniuc
parent
e916201004
commit
6300b03414
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@ -1,8 +1,9 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Advanced Micro Devices, Inc.
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* Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
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* Copyright (C) 2009 Rudolf Marek <r.marek@assembler.cz>
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* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -23,9 +24,230 @@
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#include <cpu/x86/msr.h>
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#include <arch/acpigen.h>
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#include <cpu/amd/powernow.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <cpu/amd/amdfam10_sysconf.h>
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#include <arch/cpu.h>
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#include <northbridge/amd/amdht/AsPsDefs.h>
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static void write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u32 *pstate_power,
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u32 *pstate_latency, u32 *pstate_control,
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u32 *pstate_status, int coreID,
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u32 pcontrol_blk, u8 plen, u8 onlyBSP)
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{
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int i;
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if ((onlyBSP) && (coreID != 0)) {
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plen = 0;
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pcontrol_blk = 0;
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}
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acpigen_write_processor(coreID, pcontrol_blk, plen);
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acpigen_write_empty_PCT();
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acpigen_write_name("_PSS");
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/* add later to total sum */
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acpigen_write_package(pstate_num);
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for (i = 0;i < pstate_num; i++)
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acpigen_write_PSS_package(pstate_feq[i],
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pstate_power[i],
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pstate_latency[i],
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pstate_latency[i],
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pstate_control[i],
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pstate_status[i]);
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/* update the package size */
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acpigen_pop_len();
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acpigen_write_PPC(pstate_num);
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/* patch the whole Processor token length */
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acpigen_pop_len();
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}
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/*
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* For details of this algorithm, please refer to the BDKG 3.62 page 69
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*/
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static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
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{
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u8 processor_brand[49];
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u32 *v;
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struct cpuid_result cpuid1;
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u16 Pstate_feq[10];
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u32 Pstate_power[10];
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u32 Pstate_latency[10];
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u32 Pstate_control[10];
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u32 Pstate_status[10];
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u8 Pstate_num;
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u8 cmp_cap;
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u8 index;
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msr_t msr;
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/* Get the Processor Brand String using cpuid(0x8000000x) command x=2,3,4 */
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cpuid1 = cpuid(0x80000002);
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v = (u32 *) processor_brand;
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v[0] = cpuid1.eax;
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v[1] = cpuid1.ebx;
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v[2] = cpuid1.ecx;
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v[3] = cpuid1.edx;
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cpuid1 = cpuid(0x80000003);
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v[4] = cpuid1.eax;
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v[5] = cpuid1.ebx;
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v[6] = cpuid1.ecx;
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v[7] = cpuid1.edx;
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cpuid1 = cpuid(0x80000004);
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v[8] = cpuid1.eax;
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v[9] = cpuid1.ebx;
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v[10] = cpuid1.ecx;
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v[11] = cpuid1.edx;
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processor_brand[48] = 0;
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printk(BIOS_INFO, "processor_brand=%s\n", processor_brand);
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/*
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* Based on the CPU socket type,cmp_cap and pwr_lmt , get the power limit.
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* socket_type : 0x10 SocketF; 0x11 AM2/ASB1 ; 0x12 S1G1
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* cmp_cap : 0x0 SingleCore ; 0x1 DualCore ; 0x2 TripleCore ; 0x3 QuadCore ; 0x5 QuintupleCore ; 0x6 HexCore
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*/
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printk(BIOS_INFO, "Pstates Algorithm ...\n");
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cmp_cap =
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(pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xE8) &
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0x7000) >> 12;
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Pstate_num = 0;
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/* See if the CPUID(0x80000007) returned EDX[7]==1b */
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cpuid1 = cpuid(0x80000007);
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if ((cpuid1.edx & 0x80) != 0x80) {
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printk(BIOS_INFO, "No valid set of P-states\n");
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goto write_pstates;
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}
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uint32_t dtemp;
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uint8_t pviModeFlag;
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uint8_t Pstate_max;
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uint8_t cpufid;
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uint8_t cpudid;
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uint8_t cpuvid;
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uint8_t cpuidd;
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uint8_t cpuidv;
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uint8_t power_step_up;
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uint8_t power_step_down;
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uint8_t pll_lock_time;
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uint32_t expanded_cpuidv;
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uint32_t core_frequency;
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uint32_t core_power;
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uint32_t core_latency;
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uint32_t core_voltage; /* multiplied by 10000 */
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/* Determine if this is a PVI or SVI system */
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dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xA0);
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if (dtemp & PVI_MODE)
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pviModeFlag = 1;
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else
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pviModeFlag = 0;
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/* Get PSmax's index */
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msr = rdmsr(0xC0010061);
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Pstate_max = (uint8_t) ((msr.lo >> PS_MAX_VAL_SHFT) & BIT_MASK_3);
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/* Determine if all enabled Pstates have the same fidvid */
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uint8_t i;
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uint8_t cpufid_prev = (rdmsr(0xC0010064).lo & 0x3f);
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uint8_t all_enabled_cores_have_same_cpufid = 1;
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for (i = 1; i < Pstate_max; i++) {
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cpufid = rdmsr(0xC0010064 + i).lo & 0x3f;
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if (cpufid != cpufid_prev) {
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all_enabled_cores_have_same_cpufid = 0;
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break;
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}
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}
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/* Populate tables with all Pstate information */
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for (Pstate_num = 0; Pstate_num < Pstate_max; Pstate_num++) {
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/* Get power state information */
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msr = rdmsr(0xC0010064 + Pstate_num);
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cpufid = (msr.lo & 0x3f);
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cpudid = (msr.lo & 0x1c0) >> 6;
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cpuvid = (msr.lo & 0xfe00) >> 9;
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cpuidd = (msr.hi & 0xff);
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cpuidv = (msr.hi & 0x300) >> 8;
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core_frequency = (100 * (cpufid + 0x10)) / (0x01 << cpudid);
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if (pviModeFlag) {
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if (cpuvid >= 0x20) {
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core_voltage = 7625 - (((cpuvid - 0x20) * 10000) / 80);
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}
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else {
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core_voltage = 15500 - ((cpuvid * 10000) / 40);
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}
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}
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else {
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cpuvid = cpuvid & 0x7f;
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if (cpuvid >= 0x7c)
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core_voltage = 0;
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else
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core_voltage = 15500 - ((cpuvid * 10000) / 80);
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}
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switch (cpuidv) {
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case 0x0:
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expanded_cpuidv = 1;
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break;
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case 0x1:
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expanded_cpuidv = 10;
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break;
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case 0x2:
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expanded_cpuidv = 100;
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break;
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case 0x3:
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expanded_cpuidv = 1000;
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break;
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}
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core_power = (core_voltage * cpuidd) / (expanded_cpuidv * 10);
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/* Calculate transition latency */
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dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xD4);
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power_step_up = (dtemp & 0xf000000) >> 24;
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power_step_down = (dtemp & 0xf00000) >> 20;
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dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xA0);
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pll_lock_time = (pll_lock_time & 0x3800) >> 11;
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if (all_enabled_cores_have_same_cpufid)
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core_latency = ((12 * power_step_down) + power_step_up) / 1000;
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else
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core_latency = (12 * (power_step_down + power_step_up) / 1000)
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+ pll_lock_time;
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Pstate_feq[Pstate_num] = core_frequency;
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Pstate_power[Pstate_num] = core_power;
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Pstate_latency[Pstate_num] = core_latency;
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Pstate_control[Pstate_num] = Pstate_num;
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Pstate_status[Pstate_num] = Pstate_num;
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}
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/* Print Pstate frequency, power, and latency */
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for (index = 0; index < Pstate_num; index++) {
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printk(BIOS_INFO, "Pstate_freq[%d] = %dMHz\t", index,
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Pstate_feq[index]);
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printk(BIOS_INFO, "Pstate_power[%d] = %dmw\n", index,
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Pstate_power[index]);
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printk(BIOS_INFO, "Pstate_latency[%d] = %dus\n", index,
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Pstate_latency[index]);
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}
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write_pstates:
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for (index = 0; index < (cmp_cap + 1); index++)
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write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_power,
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Pstate_latency, Pstate_control, Pstate_status,
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index, pcontrol_blk, plen, onlyBSP);
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}
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/* FIXME: this should be implemented but right now all boards hardcode it. */
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void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
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{
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return;
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char pscope[] = "\\_PR";
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acpigen_write_scope(pscope);
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pstates_algorithm(pcontrol_blk, plen, onlyBSP);
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acpigen_pop_len();
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}
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