{cpu,soc}/intel: replace AES-NI locking by common implemenation call

Deduplicate code by using the new common cpu code implementation of
AES-NI locking.

Change-Id: I7ab2d3839ecb758335ef8cc6a0c0c7103db0fa50
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Michael Niewöhner 2020-10-11 17:34:54 +02:00
parent 2ac743330c
commit 63032439f4
9 changed files with 12 additions and 46 deletions

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@ -216,11 +216,7 @@ static void model_2065x_init(struct device *cpu)
/* Set virtualization based on Kconfig option */ /* Set virtualization based on Kconfig option */
set_vmx_and_lock(); set_vmx_and_lock();
if (!intel_ht_sibling()) { set_aesni_lock();
/* Lock AES-NI only if supported */
if (cpuid_ecx(1) & (1 << 25))
msr_set(MSR_FEATURE_CONFIG, BIT(0));
}
/* Configure Enhanced SpeedStep and Thermal Sensors */ /* Configure Enhanced SpeedStep and Thermal Sensors */
configure_misc(); configure_misc();

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@ -470,11 +470,7 @@ static void model_206ax_init(struct device *cpu)
/* Thermal throttle activation offset */ /* Thermal throttle activation offset */
configure_thermal_target(); configure_thermal_target();
if (!intel_ht_sibling()) { set_aesni_lock();
/* Lock AES-NI only if supported */
if (cpuid_ecx(1) & (1 << 25))
msr_set(MSR_FEATURE_CONFIG, BIT(0));
}
/* Enable Direct Cache Access */ /* Enable Direct Cache Access */
configure_dca_cap(); configure_dca_cap();

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@ -6,6 +6,7 @@
*/ */
#define MSR_FEATURE_CONFIG 0x13c #define MSR_FEATURE_CONFIG 0x13c
#define AESNI_DISABLE (1 << 1)
#define AESNI_LOCK (1 << 0) #define AESNI_LOCK (1 << 0)
#endif /* CPU_INTEL_MSR_H */ #endif /* CPU_INTEL_MSR_H */

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@ -9,6 +9,7 @@
#include <cpu/x86/mp.h> #include <cpu/x86/mp.h>
#include <cpu/intel/microcode.h> #include <cpu/intel/microcode.h>
#include <cpu/intel/turbo.h> #include <cpu/intel/turbo.h>
#include <cpu/intel/common/common.h>
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
@ -43,12 +44,6 @@ static const struct reg_script core_msr_script[] = {
#endif #endif
/* Disable C1E */ /* Disable C1E */
REG_MSR_RMW(MSR_POWER_CTL, ~POWER_CTL_C1E_MASK, 0), REG_MSR_RMW(MSR_POWER_CTL, ~POWER_CTL_C1E_MASK, 0),
/*
* Enable and Lock the Advanced Encryption Standard (AES-NI)
* feature register
*/
REG_MSR_RMW(MSR_FEATURE_CONFIG, ~FEATURE_CONFIG_RESERVED_MASK,
FEATURE_CONFIG_LOCK),
REG_SCRIPT_END REG_SCRIPT_END
}; };
@ -62,6 +57,9 @@ void soc_core_init(struct device *cpu)
/* Set core MSRs */ /* Set core MSRs */
reg_script_run(core_msr_script); reg_script_run(core_msr_script);
set_aesni_lock();
/* /*
* Enable ACPI PM timer emulation, which also lets microcode know * Enable ACPI PM timer emulation, which also lets microcode know
* location of ACPI_BASE_ADDRESS. This also enables other features * location of ACPI_BASE_ADDRESS. This also enables other features

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@ -3,6 +3,7 @@
#include <acpi/acpigen.h> #include <acpi/acpigen.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/intel/turbo.h> #include <cpu/intel/turbo.h>
#include <cpu/intel/common/common.h>
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <intelblocks/cpulib.h> #include <intelblocks/cpulib.h>

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@ -24,9 +24,6 @@
#define EMULATE_DELAY_OFFSET_VALUE 20 #define EMULATE_DELAY_OFFSET_VALUE 20
#define EMULATE_PM_TMR_EN (1 << 16) #define EMULATE_PM_TMR_EN (1 << 16)
#define EMULATE_DELAY_VALUE 0x13 #define EMULATE_DELAY_VALUE 0x13
#define MSR_FEATURE_CONFIG 0x13c
#define FEATURE_CONFIG_RESERVED_MASK 0x3ULL
#define FEATURE_CONFIG_LOCK (1 << 0)
#define SMM_MCA_CAP_MSR 0x17d #define SMM_MCA_CAP_MSR 0x17d
#define SMM_CPU_SVRSTR_BIT 57 #define SMM_CPU_SVRSTR_BIT 57
#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) #define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32))

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@ -34,6 +34,7 @@ config CPU_SPECIFIC_OPTIONS
select TSC_SYNC_MFENCE select TSC_SYNC_MFENCE
select UDELAY_TSC select UDELAY_TSC
select UDK_2015_BINDING select UDK_2015_BINDING
select CPU_INTEL_COMMON
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select SUPPORT_CPU_UCODE_IN_CBFS select SUPPORT_CPU_UCODE_IN_CBFS

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@ -9,6 +9,7 @@
#include <cpu/intel/smm_reloc.h> #include <cpu/intel/smm_reloc.h>
#include <cpu/intel/em64t100_save_state.h> #include <cpu/intel/em64t100_save_state.h>
#include <cpu/intel/turbo.h> #include <cpu/intel/turbo.h>
#include <cpu/intel/common/common.h>
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <intelblocks/cpulib.h> #include <intelblocks/cpulib.h>
@ -59,12 +60,7 @@ static void denverton_core_init(struct device *cpu)
msr.lo |= FAST_STRINGS_ENABLE_BIT; msr.lo |= FAST_STRINGS_ENABLE_BIT;
wrmsr(IA32_MISC_ENABLE, msr); wrmsr(IA32_MISC_ENABLE, msr);
/* Lock AES-NI only if supported */ set_aesni_lock();
if (cpuid_ecx(1) & (1 << 25)) {
msr = rdmsr(MSR_FEATURE_CONFIG);
msr.lo |= FEATURE_CONFIG_LOCK; /* Lock AES-NI */
wrmsr(MSR_FEATURE_CONFIG, msr);
}
/* Enable Turbo */ /* Enable Turbo */
enable_turbo(); enable_turbo();

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@ -186,25 +186,6 @@ static void enable_pm_timer_emulation(void)
wrmsr(MSR_EMULATE_PM_TIMER, msr); wrmsr(MSR_EMULATE_PM_TIMER, msr);
} }
/*
* Lock AES-NI (MSR_FEATURE_CONFIG) to prevent unintended disabling
* as suggested in Intel document 325384-070US.
*/
static void cpu_lock_aesni(void)
{
msr_t msr;
/* Only run once per core as specified in the MSR datasheet */
if (intel_ht_sibling())
return;
msr = rdmsr(MSR_FEATURE_CONFIG);
if ((msr.lo & 1) == 0) {
msr.lo |= 1;
wrmsr(MSR_FEATURE_CONFIG, msr);
}
}
/* All CPUs including BSP will run the following function. */ /* All CPUs including BSP will run the following function. */
void soc_core_init(struct device *cpu) void soc_core_init(struct device *cpu)
{ {
@ -227,8 +208,7 @@ void soc_core_init(struct device *cpu)
/* Configure Intel Speed Shift */ /* Configure Intel Speed Shift */
configure_isst(); configure_isst();
/* Lock AES-NI MSR */ set_aesni_lock();
cpu_lock_aesni();
/* Enable ACPI Timer Emulation via MSR 0x121 */ /* Enable ACPI Timer Emulation via MSR 0x121 */
enable_pm_timer_emulation(); enable_pm_timer_emulation();