mb/intel/jasperlake_rvp: Add initial mainboard code
This is a initial mainboard code aimed to serve as base for
further mainboard check-ins.
This is a copy patch from icelake_rvp as on commit ID:
I64db2460115f5fb35ca197b83440f8ee47470761
Below are the changes done over the copy patch:
1. Rename "Icelake" with "Jasperlake".
2. Replace "icelake_rvp" with "jasperlake_rvp".
3. Rename "icl" with "jsl".
4. Remove unwanted SPD file, add empty SPD as
placeholder.
5. Replace "soc/intel/icelake" with "soc/intel/tigerlake"
as tigerlake SOC hosts jasperlake code as well.
6. Empty romstage_fsp_params.c, to fill it later with
SOC specific config.
7. Empty GPIO configuration, to be filled as per board.
8. Change copyright year to 2019.
9. Add two board support namely BOARD_INTEL_JASPERLAKE_RVP
and BOARD_INTEL_JASPERLAKE_RVP_EXT_EC
10. Replace icl_u and icl_y variant with jslrvp variant.
11. Remove basebord gpio.c and rely on variant override.
12. Remove HDA verb table and config support.
Changes to follow on top of this:
1. Add correct memory parameters, add SPDs.
2. Clean up devicetree as per jasperlake SOC.
3. Add GPIO support.
4. Update chromeos.fmd to make 10MB BIOS region.
TEST=Build jasperlake rvp board
Change-Id: I3314215807959b7348b71933fbba98e6487c0632
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
This commit is contained in:
Aamir Bohra
Subrata Banik
parent
731e6288e6
commit
630aa4b3db
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@ -0,0 +1,53 @@
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if BOARD_INTEL_JASPERLAKE_RVP || BOARD_INTEL_JASPERLAKE_RVP_EXT_EC
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_16384
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select DRIVERS_I2C_HID
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select DRIVERS_I2C_GENERIC
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select DRIVERS_USB_ACPI
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select EC_ACPI
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select GENERIC_SPD_BIN
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_USES_IFD_EC_REGION
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select SOC_INTEL_JASPERLAKE
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config MAINBOARD_DIR
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string
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default "intel/jasperlake_rvp"
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config VARIANT_DIR
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string
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default "jslrvp" if BOARD_INTEL_JASPERLAKE_RVP || BOARD_INTEL_JASPERLAKE_RVP_EXT_EC
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config MAINBOARD_PART_NUMBER
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string
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default "blackwall"
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config MAINBOARD_FAMILY
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string
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default "Intel_jasperlake_rvp"
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config MAX_CPUS
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int
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default 8
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config DEVICETREE
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string
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default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
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config DIMM_SPD_SIZE
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int
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default 512
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config VBOOT
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select VBOOT_LID_SWITCH
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select VBOOT_MOCK_SECDATA
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config UART_FOR_CONSOLE
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int
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default 2
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endif
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@ -0,0 +1,5 @@
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config BOARD_INTEL_JASPERLAKE_RVP
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bool "Jasperlake DDR4/LPDDR4 RVP"
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config BOARD_INTEL_JASPERLAKE_RVP_EXT_EC
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bool "Jasperlake DDR4/LPDDR4 RVP with Chrome EC"
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@ -0,0 +1,35 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2019 Intel Corporation.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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subdirs-y += spd
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bootblock-y += bootblock.c
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bootblock-$(CONFIG_CHROMEOS) += chromeos.c
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verstage-$(CONFIG_CHROMEOS) += chromeos.c
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romstage-$(CONFIG_CHROMEOS) += chromeos.c
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romstage-y += romstage_fsp_params.c
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romstage-y += board_id.c
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ramstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-y += mainboard.c
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ramstage-y += board_id.c
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subdirs-y += ../common
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subdirs-y += variants/baseboard
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
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subdirs-y += variants/$(VARIANT_DIR)
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@ -0,0 +1,24 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#if CONFIG(EC_GOOGLE_CHROMEEC)
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Scope (\_SB)
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{
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Device (PWRB)
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{
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Name (_HID, EisaId ("PNP0C0C"))
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}
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}
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#endif
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@ -0,0 +1,52 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <boardid.h>
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#include <ec/acpi/ec.h>
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#include <ec/google/chromeec/ec.h>
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#include <stdint.h>
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#include "board_id.h"
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static uint32_t get_board_id_via_ext_ec(void)
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{
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uint32_t id = BOARD_ID_INIT;
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if (google_chromeec_get_board_version(&id))
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id = BOARD_ID_UNKNOWN;
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return id;
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}
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/* Get Board ID via EC I/O port write/read */
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int get_board_id(void)
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{
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MAYBE_STATIC_NONZERO int id = -1;
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if (id < 0) {
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if (CONFIG(EC_GOOGLE_CHROMEEC)) {
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id = get_board_id_via_ext_ec();
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} else {
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uint8_t buffer[2];
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uint8_t index;
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if (send_ec_command(EC_FAB_ID_CMD) == 0) {
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for (index = 0; index < sizeof(buffer); index++)
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buffer[index] = recv_ec_data();
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id = (buffer[0] << 8) | buffer[1];
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}
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}
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}
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return id;
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}
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@ -0,0 +1,30 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _MAINBOARD_COMMON_BOARD_ID_H_
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#define _MAINBOARD_COMMON_BOARD_ID_H_
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#include <stdint.h>
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/* Board/FAB ID Command */
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#define EC_FAB_ID_CMD 0x0D
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/*
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* Returns board information (board id[15:8] and
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* Fab info[7:0]) on success and < 0 on error
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*/
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int get_board_id(void);
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#endif /* _MAINBOARD_COMMON_BOARD_ID_H_ */
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@ -0,0 +1,6 @@
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Vendor name: Intel
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Board name: Jasperlake rvp
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Category: eval
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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@ -0,0 +1,28 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <bootblock_common.h>
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#include <soc/gpio.h>
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void bootblock_mainboard_init(void)
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{
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const struct pad_config *pads;
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size_t num;
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pads = variant_early_gpio_table(&num);
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gpio_configure_pads(pads, num);
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}
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@ -0,0 +1,57 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <boot/coreboot_tables.h>
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#include <gpio.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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struct lb_gpio chromeos_gpios[] = {
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{-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
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{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
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{-1, ACTIVE_HIGH, 0, "power"},
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{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
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};
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lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
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}
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int get_lid_switch(void)
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{
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/* Lid always open */
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return 1;
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}
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int get_recovery_mode_switch(void)
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{
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return 0;
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}
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int get_write_protect_state(void)
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{
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/* No write protect */
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return 0;
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}
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void mainboard_chromeos_acpi_generate(void)
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{
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const struct cros_gpio *gpios;
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size_t num;
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gpios = variant_cros_gpios(&num);
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chromeos_acpi_gpio_generate(gpios, num);
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}
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FLASH@0xff000000 0x1000000 {
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SI_ALL@0x0 0x3F0000 {
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SI_DESC@0x0 0x1000
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SI_EC@0x1000 0x80000
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SI_ME@0x81000 0x36F000
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}
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SI_BIOS@0x400000 0xC00000 {
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RW_SECTION_A@0x0 0x2d0000 {
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VBLOCK_A@0x0 0x10000
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FW_MAIN_A(CBFS)@0x10000 0x2bffc0
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RW_FWID_A@0x2cffc0 0x40
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}
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RW_SECTION_B@0x2d0000 0x2d0000 {
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VBLOCK_B@0x0 0x10000
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FW_MAIN_B(CBFS)@0x10000 0x2bffc0
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RW_FWID_B@0x2cffc0 0x40
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}
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RW_MISC@0x5a0000 0x30000 {
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UNIFIED_MRC_CACHE@0x0 0x20000 {
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RECOVERY_MRC_CACHE@0x0 0x10000
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RW_MRC_CACHE@0x10000 0x10000
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}
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RW_ELOG(PRESERVE)@0x20000 0x4000
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RW_SHARED@0x24000 0x4000 {
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SHARED_DATA@0x0 0x2000
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VBLOCK_DEV@0x2000 0x2000
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}
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RW_VPD(PRESERVE)@0x28000 0x2000
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RW_NVRAM(PRESERVE)@0x2a000 0x6000
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}
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SMMSTORE(PRESERVE)@0x5d0000 0x40000
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RW_LEGACY(CBFS)@0x610000 0x1c0000
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WP_RO@0x7d0000 0x430000 {
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RO_VPD(PRESERVE)@0x0 0x4000
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RO_SECTION@0x4000 0x42c000 {
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FMAP@0x0 0x800
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RO_FRID@0x800 0x40
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RO_FRID_PAD@0x840 0x7c0
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GBB@0x1000 0xef000
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COREBOOT(CBFS)@0xf0000 0x33c000
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}
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}
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}
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}
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@ -0,0 +1,68 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Intel Corporation
|
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*
|
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
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*/
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#include <arch/acpi.h>
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#include <baseboard/ec.h>
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#include <baseboard/gpio.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x02, /* DSDT revision: ACPI v2.0 and up */
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20110725 /* OEM revision */
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)
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{
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/* Some generic macros */
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#include <soc/intel/tigerlake/acpi/platform.asl>
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/* global NVS and variables */
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#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
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/* CPU */
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#include <cpu/intel/common/acpi/cpu.asl>
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <soc/intel/tigerlake/acpi/northbridge.asl>
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#include <soc/intel/tigerlake/acpi/southbridge.asl>
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}
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}
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#if CONFIG(CHROMEOS)
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/* Chrome OS specific */
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#include <vendorcode/google/chromeos/acpi/chromeos.asl>
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#endif
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#if CONFIG(EC_GOOGLE_CHROMEEC)
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/* Chrome OS Embedded Controller */
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Scope (\_SB.PCI0.LPCB)
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{
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/* ACPI code for EC SuperIO functions */
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#include <ec/google/chromeec/acpi/superio.asl>
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/* ACPI code for EC functions */
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#include <ec/google/chromeec/acpi/ec.asl>
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}
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#endif
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/* Chipset specific sleep states */
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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/* Mainboard specific */
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#include "acpi/mainboard.asl"
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|
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}
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@ -0,0 +1,39 @@
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/*
|
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* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
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#include <baseboard/gpio.h>
|
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#include <baseboard/variants.h>
|
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#include <device/device.h>
|
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#include <soc/gpio.h>
|
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#include <vendorcode/google/chromeos/chromeos.h>
|
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|
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static void mainboard_init(void *chip_info)
|
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{
|
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const struct pad_config *pads;
|
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size_t num;
|
||||
|
||||
pads = variant_gpio_table(&num);
|
||||
gpio_configure_pads(pads, num);
|
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}
|
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|
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static void mainboard_enable(struct device *dev)
|
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{
|
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dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
|
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}
|
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|
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struct chip_operations mainboard_ops = {
|
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.init = mainboard_init,
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <fsp/api.h>
|
||||
#include <soc/romstage.h>
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *mupd)
|
||||
{
|
||||
/* ToDo : Fill FSP-M memory params */
|
||||
}
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2019 Intel Corporation.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
|
||||
romstage-y += spd_util.c
|
||||
|
||||
SPD_BIN = $(obj)/spd.bin
|
||||
|
||||
SPD_SOURCES = empty # 0b000
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef MAINBOARD_SPD_H
|
||||
#define MAINBOARD_SPD_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define RCOMP_TARGET_PARAMS 0x5
|
||||
|
||||
void mainboard_fill_dq_map_ch0(u8 *dq_map_ptr);
|
||||
void mainboard_fill_dq_map_ch1(u8 *dq_map_ptr);
|
||||
void mainboard_fill_dqs_map_ch0(u8 *dqs_map_ptr);
|
||||
void mainboard_fill_dqs_map_ch1(u8 *dqs_map_ptr);
|
||||
void mainboard_fill_rcomp_res_data(u16 *rcomp_ptr);
|
||||
void mainboard_fill_rcomp_strength_data(u16 *rcomp_strength_ptr);
|
||||
#endif
|
||||
|
|
@ -0,0 +1,133 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/cpu.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "../board_id.h"
|
||||
#include "spd.h"
|
||||
|
||||
enum jsl_dimm_type {
|
||||
jsl_u_ddr4 = 0,
|
||||
jsl_u_lpddr4 = 1,
|
||||
jsl_u_lpddr4_type_3 = 4,
|
||||
jsl_y_lpddr4 = 6
|
||||
};
|
||||
|
||||
void mainboard_fill_dq_map_ch0(u8 *dq_map_ptr)
|
||||
{
|
||||
/* DQ byte map Ch0 */
|
||||
const u8 dq_map[12] = {
|
||||
0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
|
||||
|
||||
memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
|
||||
}
|
||||
|
||||
static uint8_t get_spd_index(void)
|
||||
{
|
||||
return get_board_id() & 0x7;
|
||||
}
|
||||
|
||||
void mainboard_fill_dq_map_ch1(u8 *dq_map_ptr)
|
||||
{
|
||||
const u8 dq_map[12] = {
|
||||
0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
|
||||
|
||||
memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
|
||||
}
|
||||
|
||||
void mainboard_fill_dqs_map_ch0(u8 *dqs_map_ptr)
|
||||
{
|
||||
/* DQS CPU<>DRAM map Ch0 */
|
||||
const u8 dqs_map_u_ddr[8] = { 2, 0, 1, 3, 6, 4, 7, 5 };
|
||||
const u8 dqs_map_u_lpddr[8] = { 2, 3, 0, 1, 7, 6, 4, 5 };
|
||||
const u8 dqs_map_u_lpddr_type_3[8] = { 2, 3, 1, 0, 7, 6, 4, 5 };
|
||||
const u8 dqs_map_y_lpddr[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
|
||||
|
||||
switch (get_spd_index()) {
|
||||
case jsl_u_ddr4:
|
||||
memcpy(dqs_map_ptr, dqs_map_u_ddr, sizeof(dqs_map_u_ddr));
|
||||
break;
|
||||
case jsl_u_lpddr4:
|
||||
memcpy(dqs_map_ptr, dqs_map_u_lpddr, sizeof(dqs_map_u_lpddr));
|
||||
break;
|
||||
case jsl_u_lpddr4_type_3:
|
||||
memcpy(dqs_map_ptr, dqs_map_u_lpddr_type_3,
|
||||
sizeof(dqs_map_u_lpddr_type_3));
|
||||
break;
|
||||
case jsl_y_lpddr4:
|
||||
memcpy(dqs_map_ptr, dqs_map_y_lpddr, sizeof(dqs_map_y_lpddr));
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void mainboard_fill_dqs_map_ch1(u8 *dqs_map_ptr)
|
||||
{
|
||||
/* DQS CPU<>DRAM map Ch1 */
|
||||
const u8 dqs_map_u_ddr[8] = { 1, 3, 2, 0, 5, 7, 6, 4 };
|
||||
const u8 dqs_map_u_lpddr[8] = { 1, 0, 3, 2, 5, 4, 7, 6 };
|
||||
const u8 dqs_map_y_lpddr[8] = { 0, 1, 2, 3, 5, 4, 7, 6 };
|
||||
|
||||
switch (get_spd_index()) {
|
||||
case jsl_u_ddr4:
|
||||
memcpy(dqs_map_ptr, dqs_map_u_ddr, sizeof(dqs_map_u_ddr));
|
||||
break;
|
||||
case jsl_u_lpddr4:
|
||||
case jsl_u_lpddr4_type_3:
|
||||
memcpy(dqs_map_ptr, dqs_map_u_lpddr, sizeof(dqs_map_u_lpddr));
|
||||
break;
|
||||
case jsl_y_lpddr4:
|
||||
memcpy(dqs_map_ptr, dqs_map_y_lpddr, sizeof(dqs_map_y_lpddr));
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void mainboard_fill_rcomp_res_data(u16 *rcomp_ptr)
|
||||
{
|
||||
/* Rcomp resistor */
|
||||
const u16 RcompResistor[3] = { 100, 100, 100 };
|
||||
memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor));
|
||||
}
|
||||
|
||||
void mainboard_fill_rcomp_strength_data(u16 *rcomp_strength_ptr)
|
||||
{
|
||||
/* Rcomp target */
|
||||
static const u16 RcompTarget_DDR4[RCOMP_TARGET_PARAMS] = {
|
||||
100, 33, 32, 33, 28 };
|
||||
static const u16 RcompTarget_LPDDR4_Ax[RCOMP_TARGET_PARAMS] = {
|
||||
80, 40, 40, 40, 30 };
|
||||
|
||||
switch (get_spd_index()) {
|
||||
case jsl_u_ddr4:
|
||||
memcpy(rcomp_strength_ptr, RcompTarget_DDR4,
|
||||
sizeof(RcompTarget_DDR4));
|
||||
break;
|
||||
case jsl_y_lpddr4:
|
||||
case jsl_u_lpddr4:
|
||||
case jsl_u_lpddr4_type_3:
|
||||
memcpy(rcomp_strength_ptr, RcompTarget_LPDDR4_Ax,
|
||||
sizeof(RcompTarget_LPDDR4_Ax));
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,80 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __BASEBOARD_EC_H__
|
||||
#define __BASEBOARD_EC_H__
|
||||
|
||||
#include <ec/ec.h>
|
||||
#include <ec/google/chromeec/ec_commands.h>
|
||||
#include <baseboard/gpio.h>
|
||||
|
||||
#define MAINBOARD_EC_SCI_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))
|
||||
|
||||
#define MAINBOARD_EC_SMI_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
|
||||
|
||||
/* EC can wake from S5 with lid or power button */
|
||||
#define MAINBOARD_EC_S5_WAKE_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
|
||||
|
||||
/*
|
||||
* EC can wake from S3 with lid or power button or key press or
|
||||
* mode change event.
|
||||
*/
|
||||
#define MAINBOARD_EC_S3_WAKE_EVENTS \
|
||||
(MAINBOARD_EC_S5_WAKE_EVENTS |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
|
||||
|
||||
/* Log EC wake events plus EC shutdown events */
|
||||
#define MAINBOARD_EC_LOG_EVENTS \
|
||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
|
||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
|
||||
|
||||
/*
|
||||
* ACPI related definitions for ASL code.
|
||||
*/
|
||||
|
||||
/* Enable EC backed ALS device in ACPI */
|
||||
#define EC_ENABLE_ALS_DEVICE
|
||||
|
||||
/* Enable EC backed PD MCU device in ACPI */
|
||||
#define EC_ENABLE_PD_MCU_DEVICE
|
||||
|
||||
/* Enable LID switch and provide wake pin for EC */
|
||||
#define EC_ENABLE_LID_SWITCH
|
||||
#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
|
||||
|
||||
#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
|
||||
#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
|
||||
#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
|
||||
|
||||
#endif /* __BASEBOARD_EC_H__ */
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __BASEBOARD_GPIO_H__
|
||||
#define __BASEBOARD_GPIO_H__
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
/* eSPI virtual wire reporting */
|
||||
#define EC_SCI_GPI GPE0_ESPI
|
||||
|
||||
/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
|
||||
#define GPE_EC_WAKE GPE0_LAN_WAK
|
||||
|
||||
#endif /* __BASEBOARD_GPIO_H__ */
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __BASEBOARD_VARIANTS_H__
|
||||
#define __BASEBOARD_VARIANTS_H__
|
||||
|
||||
#include <soc/gpio.h>
|
||||
#include <stdint.h>
|
||||
#include <vendorcode/google/chromeos/chromeos.h>
|
||||
|
||||
/* The next set of functions return the gpio table and fill in the number of
|
||||
* entries for each table. */
|
||||
|
||||
const struct pad_config *variant_gpio_table(size_t *num);
|
||||
const struct pad_config *variant_early_gpio_table(size_t *num);
|
||||
const struct cros_gpio *variant_cros_gpios(size_t *num);
|
||||
|
||||
#endif /*__BASEBOARD_VARIANTS_H__ */
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2019 Intel Corporation.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
|
||||
bootblock-y += gpio.c
|
||||
|
||||
ramstage-y += gpio.c
|
||||
|
|
@ -0,0 +1,337 @@
|
|||
chip soc/intel/tigerlake
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
||||
# GPE configuration
|
||||
# Note that GPE events called out in ASL code rely on this
|
||||
# route. i.e. If this route changes then the affected GPE
|
||||
# offset bits also need to be changed.
|
||||
register "gpe0_dw0" = "GPP_B"
|
||||
register "gpe0_dw1" = "GPP_D"
|
||||
register "gpe0_dw2" = "GPP_E"
|
||||
|
||||
# FSP configuration
|
||||
register "SaGv" = "SaGv_Enabled"
|
||||
register "SmbusEnable" = "1"
|
||||
register "ScsEmmcHs400Enabled" = "1"
|
||||
register "SdCardPowerEnableActiveHigh" = "1"
|
||||
|
||||
register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1
|
||||
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB2 WWAN
|
||||
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Bluetooth
|
||||
register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # Type-C Port1
|
||||
register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-C Port2
|
||||
register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3
|
||||
register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" # Type-C Port4
|
||||
register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2
|
||||
register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB2 Type A port1
|
||||
register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # USB2 Type A port2
|
||||
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WLAN
|
||||
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED
|
||||
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED
|
||||
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # UNUSED
|
||||
|
||||
# Enable Pch iSCLK
|
||||
register "pch_isclk" = "1"
|
||||
|
||||
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
|
||||
register "gen1_dec" = "0x00fc0801"
|
||||
register "gen2_dec" = "0x000c0201"
|
||||
# EC memory map range is 0x900-0x9ff
|
||||
register "gen3_dec" = "0x00fc0901"
|
||||
|
||||
register "PchHdaDspEnable" = "1"
|
||||
register "PchHdaAudioLinkHda" = "1"
|
||||
|
||||
register "PcieRpEnable[0]" = "1"
|
||||
register "PcieRpEnable[1]" = "0"
|
||||
register "PcieRpEnable[2]" = "0"
|
||||
register "PcieRpEnable[3]" = "0"
|
||||
register "PcieRpEnable[4]" = "1"
|
||||
register "PcieRpEnable[5]" = "0"
|
||||
register "PcieRpEnable[6]" = "0"
|
||||
register "PcieRpEnable[7]" = "0"
|
||||
register "PcieRpEnable[8]" = "1"
|
||||
register "PcieRpEnable[9]" = "0"
|
||||
register "PcieRpEnable[10]" = "0"
|
||||
register "PcieRpEnable[11]" = "0"
|
||||
register "PcieRpEnable[12]" = "0"
|
||||
register "PcieRpEnable[13]" = "0"
|
||||
register "PcieRpEnable[14]" = "0"
|
||||
register "PcieRpEnable[15]" = "0"
|
||||
|
||||
register "PcieClkSrcUsage[0]" = "2"
|
||||
register "PcieClkSrcUsage[1]" = "8"
|
||||
register "PcieClkSrcUsage[2]" = "0xC"
|
||||
register "PcieClkSrcUsage[3]" = "0x70"
|
||||
register "PcieClkSrcUsage[4]" = "4"
|
||||
register "PcieClkSrcUsage[5]" = "0xE"
|
||||
register "PcieClkSrcUsage[6]" = "0x80"
|
||||
register "PcieClkSrcUsage[7]" = "0x80"
|
||||
register "PcieClkSrcUsage[8]" = "0x80"
|
||||
register "PcieClkSrcUsage[9]" = "0x80"
|
||||
register "PcieClkSrcUsage[10]" = "0x80"
|
||||
register "PcieClkSrcUsage[11]" = "0x80"
|
||||
register "PcieClkSrcUsage[12]" = "0x80"
|
||||
register "PcieClkSrcUsage[13]" = "0x80"
|
||||
register "PcieClkSrcUsage[14]" = "0x80"
|
||||
register "PcieClkSrcUsage[15]" = "0x80"
|
||||
|
||||
register "PcieClkSrcClkReq[0]" = "0"
|
||||
register "PcieClkSrcClkReq[1]" = "1"
|
||||
register "PcieClkSrcClkReq[2]" = "2"
|
||||
register "PcieClkSrcClkReq[3]" = "3"
|
||||
register "PcieClkSrcClkReq[4]" = "4"
|
||||
register "PcieClkSrcClkReq[5]" = "5"
|
||||
register "PcieClkSrcClkReq[6]" = "6"
|
||||
register "PcieClkSrcClkReq[7]" = "7"
|
||||
register "PcieClkSrcClkReq[8]" = "8"
|
||||
register "PcieClkSrcClkReq[9]" = "9"
|
||||
register "PcieClkSrcClkReq[10]" = "10"
|
||||
register "PcieClkSrcClkReq[11]" = "11"
|
||||
register "PcieClkSrcClkReq[12]" = "12"
|
||||
register "PcieClkSrcClkReq[13]" = "13"
|
||||
register "PcieClkSrcClkReq[14]" = "14"
|
||||
register "PcieClkSrcClkReq[15]" = "15"
|
||||
|
||||
register "SataEnable" = "1"
|
||||
register "SataSalpSupport" = "1"
|
||||
register "SataPortsEnable[0]" = "1"
|
||||
register "SataPortsEnable[1]" = "1"
|
||||
register "SataPortsEnable[2]" = "1"
|
||||
register "SataPortsEnable[3]" = "1"
|
||||
register "SataPortsEnable[4]" = "1"
|
||||
register "SataPortsEnable[5]" = "1"
|
||||
register "SataPortsEnable[6]" = "1"
|
||||
register "SataPortsEnable[7]" = "1"
|
||||
|
||||
register "SataPortsDevSlp[0]" = "1"
|
||||
register "SataPortsDevSlp[1]" = "1"
|
||||
register "SataPortsDevSlp[2]" = "1"
|
||||
register "SataPortsDevSlp[3]" = "1"
|
||||
register "SataPortsDevSlp[4]" = "1"
|
||||
register "SataPortsDevSlp[5]" = "1"
|
||||
register "SataPortsDevSlp[6]" = "1"
|
||||
register "SataPortsDevSlp[7]" = "1"
|
||||
|
||||
register "SerialIoI2cMode" = "{
|
||||
[PchSerialIoIndexI2C0] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C1] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C2] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C3] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexI2C5] = PchSerialIoPci,
|
||||
}"
|
||||
|
||||
register "SerialIoGSpiMode" = "{
|
||||
[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexGSPI1] = PchSerialIoPci,
|
||||
[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
|
||||
}"
|
||||
|
||||
register "SerialIoGSpiCsMode" = "{
|
||||
[PchSerialIoIndexGSPI0] = 1,
|
||||
[PchSerialIoIndexGSPI1] = 1,
|
||||
[PchSerialIoIndexGSPI2] = 1,
|
||||
}"
|
||||
|
||||
register "SerialIoGSpiCsState" = "{
|
||||
[PchSerialIoIndexGSPI0] = 0,
|
||||
[PchSerialIoIndexGSPI1] = 0,
|
||||
[PchSerialIoIndexGSPI2] = 0,
|
||||
}"
|
||||
|
||||
register "SerialIoUartMode" = "{
|
||||
[PchSerialIoIndexUART0] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
|
||||
}"
|
||||
|
||||
# Enable "Intel Speed Shift Technology"
|
||||
register "speed_shift_enable" = "1"
|
||||
|
||||
# Enable DPTF
|
||||
register "dptf_enable" = "1"
|
||||
|
||||
# GPIO for SD card detect
|
||||
register "sdcard_cd_gpio" = "GPP_G5"
|
||||
|
||||
# Enable S0ix
|
||||
register "s0ix_enable" = "0"
|
||||
|
||||
register "common_soc_config" = "{
|
||||
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
|
||||
.gspi[1] = {
|
||||
.speed_mhz = 1,
|
||||
.early_init = 1,
|
||||
},
|
||||
}"
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
device pci 02.0 on end # Integrated Graphics Device
|
||||
device pci 04.0 off end # SA Thermal device
|
||||
device pci 12.0 off end # Thermal Subsystem
|
||||
device pci 12.5 off end # UFS SCS
|
||||
device pci 12.6 off end # GSPI #2
|
||||
device pci 14.0 on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Root Hub""
|
||||
register "type" = "UPC_TYPE_HUB"
|
||||
device usb 0.0 on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3/2 Type-A Left Lower""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
device usb 2.0 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""WWAN""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device usb 2.1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Bluetooth""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device usb 2.2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB C Connector 1""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
device usb 2.3 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB C Connector 2""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
device usb 2.4 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB C Connector 3""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
device usb 2.5 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB C Connector 4""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
device usb 2.6 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3/2 Type-A Left Upper""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
device usb 2.7 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Right Lower""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
device usb 2.8 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Right Upper""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
device usb 2.9 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3/2 Type-A Left Lower""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
device usb 3.0 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3/2 Type-A Left Upper""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
device usb 3.1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""WLAN""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device usb 3.2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Port Unused1""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device usb 3.3 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Port Unused2""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device usb 3.4 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Port Unused3""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device usb 3.5 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end # USB xHCI
|
||||
device pci 14.1 off end # USB xDCI (OTG)
|
||||
device pci 14.2 off end # PMC SRAM
|
||||
chip drivers/intel/wifi
|
||||
register "wake" = "GPE0_PME_B0"
|
||||
device pci 14.3 on end # CNVi wifi
|
||||
end
|
||||
device pci 14.5 on end # SDCard
|
||||
device pci 15.0 on
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""ALPS0000""
|
||||
register "generic.desc" = ""Touchpad""
|
||||
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C8_IRQ)"
|
||||
register "hid_desc_reg_offset" = "0x20"
|
||||
device i2c 2c on end
|
||||
end
|
||||
end # I2C 0
|
||||
device pci 15.1 on end # I2C #1
|
||||
device pci 15.2 on end # I2C #2
|
||||
device pci 15.3 on end # I2C #3
|
||||
device pci 16.0 on end # Management Engine Interface 1
|
||||
device pci 16.1 off end # Management Engine Interface 2
|
||||
device pci 16.2 off end # Management Engine IDE-R
|
||||
device pci 16.3 off end # Management Engine KT Redirection
|
||||
device pci 16.4 off end # Management Engine Interface 3
|
||||
device pci 16.5 off end # Management Engine Interface 4
|
||||
device pci 17.0 on end # SATA
|
||||
device pci 19.0 on end # I2C #4
|
||||
device pci 19.1 off end # I2C #5
|
||||
device pci 19.2 on end # UART #2
|
||||
device pci 1a.0 on end # eMMC
|
||||
device pci 1c.0 on
|
||||
chip drivers/intel/wifi
|
||||
register "wake" = "GPE0_PCI_EXP"
|
||||
device pci 00.0 on end
|
||||
end
|
||||
end # PCI Express Port 1 x4 SLOT1
|
||||
device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN
|
||||
device pci 1c.5 off end # PCI Express Port 6
|
||||
device pci 1c.6 off end # PCI Express Port 7
|
||||
device pci 1c.7 off end # PCI Express Port 8
|
||||
device pci 1d.0 on end # PCI Express Port 9
|
||||
device pci 1d.1 off end # PCI Express Port 10
|
||||
device pci 1d.2 off end # PCI Express Port 11
|
||||
device pci 1d.3 off end # PCI Express Port 12
|
||||
device pci 1d.4 off end # PCI Express Port 13
|
||||
device pci 1d.5 off end # PCI Express Port 14
|
||||
device pci 1d.6 off end # PCI Express Port 15
|
||||
device pci 1d.7 off end # PCI Express Port 16
|
||||
device pci 1e.0 on end # UART #0
|
||||
device pci 1e.1 off end # UART #1
|
||||
device pci 1e.2 off end # GSPI #0
|
||||
device pci 1e.3 on
|
||||
chip drivers/spi/acpi
|
||||
register "hid" = "ACPI_DT_NAMESPACE_HID"
|
||||
register "compat_string" = ""google,cr50""
|
||||
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"
|
||||
device spi 0 on end
|
||||
end
|
||||
end # GSPI #1
|
||||
device pci 1f.0 on end # eSPI Interface
|
||||
device pci 1f.1 on end # P2SB
|
||||
device pci 1f.2 on end # Power Management Controller
|
||||
device pci 1f.3 on end # Intel HDA
|
||||
device pci 1f.4 on end # SMBus
|
||||
device pci 1f.5 on end # PCH SPI
|
||||
device pci 1f.6 off end # GbE
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
#include <baseboard/variants.h>
|
||||
#include <commonlib/helpers.h>
|
||||
|
||||
/* Pad configuration in ramstage*/
|
||||
static const struct pad_config gpio_table[] = {
|
||||
/* ToDo: Fill gpio configuration */
|
||||
};
|
||||
|
||||
/* Early pad configuration in bootblock */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
/* ToDo: Fill early gpio configurations for TPM and WWAN */
|
||||
};
|
||||
|
||||
const struct pad_config *variant_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(gpio_table);
|
||||
return gpio_table;
|
||||
}
|
||||
|
||||
const struct pad_config *variant_early_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(early_gpio_table);
|
||||
return early_gpio_table;
|
||||
}
|
||||
|
||||
static const struct cros_gpio cros_gpios[] = {
|
||||
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
|
||||
};
|
||||
|
||||
const struct cros_gpio *variant_cros_gpios(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(cros_gpios);
|
||||
return cros_gpios;
|
||||
}
|
||||
Loading…
Reference in New Issue