From 631d77eca9fa60771ce71648e47f7918d6a2e397 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Wed, 21 Dec 2022 14:17:54 -0600 Subject: [PATCH] mb/google/drallion: Implement touchscreen power sequencing For touchscreens on drallion, drive the enable GPIO high starting in romstage while holding in reset, then disable the reset GPIO in ramstage. This will allow coreboot to detect the presence of i2c touchscreens during ACPI SSDT generation (implemented in a subsequent commit). BUG=b:121309055 TEST=tested with rest of patch train Change-Id: I6825345f35a7415020e77edf781139f0c9b5f875 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/71191 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- .../google/drallion/variants/drallion/gpio.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index b008427b7b..2acb35bacb 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -65,7 +65,7 @@ static const struct pad_config gpio_table[] = { /* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), /* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */ /* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), -/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 0, DEEP), /* PCH_3.3V_TS_EN */ +/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */ /* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), /* SML1ALERT# */ PAD_NC(GPP_B23, DN_20K), @@ -111,7 +111,7 @@ static const struct pad_config gpio_table[] = { /* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, UP_20K, DEEP, NF1), /* ISH_CPU_UART0_TX */ /* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), -/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 0, DEEP), /* TS_RST */ +/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* TS_RST */ /* ISH_UART0_CTS# */ PAD_CFG_GPI(GPP_D16, NONE, PLTRST), /* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, PLTRST), /* KB_DET# */ /* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, @@ -249,10 +249,16 @@ const struct pad_config *variant_early_gpio_table(size_t *num) return early_gpio_table; } +static const struct pad_config romstage_gpio_table[] = { + /* Enable touchscreen, hold in reset */ + PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */ + PAD_CFG_GPO(GPP_D15, 0, DEEP), /* TS_RST */ +}; + const struct pad_config *variant_romstage_gpio_table(size_t *num) { - *num = 0; - return NULL; + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; } static const struct cros_gpio cros_gpios[] = {