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mb/google/kahlee/treeya: Tune I2C bus 1, 2 and 3 clock 

Tune I2C bus 1, 2 and 3 clock and make them meet spec.

BUG=b:140665478
TEST==flash coreboot to the DUT and measure I2C bus 1,2,3 clock
frequency less than 400KHz

Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I6b2a51a866e57d13fe528452e4efdcf17a72317f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35298
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Peichao Wang 2019-09-09 09:10:54 +08:00 committed by Patrick Georgi
parent 203061c24a
commit 632283092c
1 changed files with 5 additions and 5 deletions
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10
src/mainboard/google/kahlee/variants/treeya/devicetree.cb
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@ -35,22 +35,22 @@ chip soc/amd/stoneyridge
register "i2c[1]" = "{
.early_init = 1,
.speed = I2C_SPEED_FAST,
.rise_time_ns = 62,
.rise_time_ns = 3,
.fall_time_ns = 2,
}"
# Enable I2C2 for trackpad, pen at 400kHz
register "i2c[2]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 170,
.fall_time_ns = 91,
.rise_time_ns = 3,
.fall_time_ns = 2,
}"
# Enable I2C3 for touchscreen at 400kHz
register "i2c[3]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 84,
.fall_time_ns = 50,
.rise_time_ns = 16,
.fall_time_ns = 8,
}"
register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | \