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mb/google/guybrush: Update GPIO configuration 

Initialize all eSPI signals including PCIE_RST0_L early for EC
communication.
- Set PCIE_RST0_L to a GPIO and set it high to release the bus.  This is
a temporary workaround until PCIE_RST_L comes up on its own.
- Make sure all GPIO muxes initialized early are re-initialized.

BUG=b:183340503
TEST=Boot Guybrush

Change-Id: I512cb8b435dc8412cd46189e741ad94e5a24699e
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51675
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Martin Roth 2021-03-21 18:45:16 -06:00 committed by Martin Roth
parent d07f724f9c
commit 632419852a
1 changed files with 11 additions and 2 deletions
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13
src/mainboard/google/guybrush/variants/baseboard/gpio.c
View File

@ -54,7 +54,8 @@ static const struct soc_amd_gpio base_gpio_table[] = {
PAD_GPO(GPIO_24, LOW), PAD_GPO(GPIO_24, LOW),
/* GPIO_25: Not available */ /* GPIO_25: Not available */
/* PCIE_RST0_L */ /* PCIE_RST0_L */
PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), /* TODO: change back to PCIE_RST_L when we figure out why PCIE_RST doesn't go high. */
PAD_GPO(GPIO_26, HIGH),
/* PCIE_RST1_L */ /* PCIE_RST1_L */
PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
/* GPIO_28: Not available */ /* GPIO_28: Not available */
@ -93,7 +94,7 @@ static const struct soc_amd_gpio base_gpio_table[] = {
PAD_GPI(GPIO_84, PULL_NONE), PAD_GPI(GPIO_84, PULL_NONE),
/* WWAN_DISABLE */ /* WWAN_DISABLE */
PAD_GPO(GPIO_85, HIGH), PAD_GPO(GPIO_85, HIGH),
/* SPI_CLK2 */ /* ESPI_SOC_CLK */
PAD_NF(GPIO_86, SPI_CLK, PULL_NONE), PAD_NF(GPIO_86, SPI_CLK, PULL_NONE),
/* RAM_ID_1 / DEV_BEEP_DATA */ /* RAM_ID_1 / DEV_BEEP_DATA */
PAD_GPI(GPIO_87, PULL_NONE), PAD_GPI(GPIO_87, PULL_NONE),
@ -116,6 +117,8 @@ static const struct soc_amd_gpio base_gpio_table[] = {
PAD_NF(GPIO_106, EMMC_SPI2_WP_L_ESPI2_D2, PULL_NONE), PAD_NF(GPIO_106, EMMC_SPI2_WP_L_ESPI2_D2, PULL_NONE),
/* ESPI1_DATA3 */ /* ESPI1_DATA3 */
PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE), PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE),
/* ESPI_ALERT_L */
PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_NONE),
/* RAM_ID_0 / DEV_BEEP_EN */ /* RAM_ID_0 / DEV_BEEP_EN */
PAD_GPI(GPIO_109, PULL_NONE), PAD_GPI(GPIO_109, PULL_NONE),
/* GPIO_110 - GPIO_112: Not available */ /* GPIO_110 - GPIO_112: Not available */
@ -169,6 +172,12 @@ static const struct soc_amd_gpio early_gpio_table[] = {
PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE),
/* I2C3_SDA */ /* I2C3_SDA */
PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE),
/* PCIE_RST0_L */
PAD_GPO(GPIO_26, HIGH),
/* ESPI_CS_L */
PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE),
/* ESPI_SOC_CLK */
PAD_NF(GPIO_86, SPI_CLK, PULL_NONE),
/* ESPI1_DATA0 */ /* ESPI1_DATA0 */
PAD_NF(GPIO_104, SPI2_DO_ESPI2_D0, PULL_NONE), PAD_NF(GPIO_104, SPI2_DO_ESPI2_D0, PULL_NONE),
/* ESPI1_DATA1 */ /* ESPI1_DATA1 */