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sb/intel/x/lpc.c: Drop `pch_disable_smm_only_flashing` 

The southbridge common SPI support already does this.

Tested on Asrock B85M Pro4, internal flashing and MRC cache still work.

Change-Id: I7ce0ca584cd3d42a10cdb74f45742f1eadc01bfa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Angel Pons 2021-02-10 13:33:17 +01:00 committed by Patrick Georgi
parent 9382f0c251
commit 6324759784
3 changed files with 0 additions and 30 deletions
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9
src/southbridge/intel/bd82x6x/lpc.c
View File

@ -404,13 +404,6 @@ static void pch_set_acpi_mode(void)
}
}
static void pch_disable_smm_only_flashing(struct device *dev)
{
printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... ");
pci_and_config8(dev, BIOS_CNTL, ~(1 << 5));
}
static void pch_fixups(struct device *dev)
{
/* Indicate DRAM init done for MRC S3 to know it can resume */
@ -557,8 +550,6 @@ static void lpc_init(struct device *dev)
/* Interrupt 9 should be level triggered (SCI) */
i8259_configure_irq_trigger(9, 1);
pch_disable_smm_only_flashing(dev);
pch_set_acpi_mode();
pch_fixups(dev);

12
src/southbridge/intel/ibexpeak/lpc.c
View File

@ -403,16 +403,6 @@ static void pch_set_acpi_mode(void)
}
}
static void pch_disable_smm_only_flashing(struct device *dev)
{
u8 reg8;
printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... ");
reg8 = pci_read_config8(dev, BIOS_CNTL);
reg8 &= ~(1 << 5);
pci_write_config8(dev, BIOS_CNTL, reg8);
}
static void pch_fixups(struct device *dev)
{
/*
@ -462,8 +452,6 @@ static void lpc_init(struct device *dev)
/* Interrupt 9 should be level triggered (SCI) */
i8259_configure_irq_trigger(9, 1);
pch_disable_smm_only_flashing(dev);
pch_set_acpi_mode();
pch_fixups(dev);

9
src/southbridge/intel/lynxpoint/lpc.c
View File

@ -475,13 +475,6 @@ static void pch_set_acpi_mode(void)
apm_control(APM_CNT_ACPI_DISABLE);
}
static void pch_disable_smm_only_flashing(struct device *dev)
{
printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... ");
pci_and_config8(dev, BIOS_CNTL, ~(1 << 5));
}
static void pch_fixups(struct device *dev)
{
/* Indicate DRAM init done for MRC S3 to know it can resume */
@ -533,8 +526,6 @@ static void lpc_init(struct device *dev)
/* Interrupt 9 should be level triggered (SCI) */
i8259_configure_irq_trigger(9, 1);
pch_disable_smm_only_flashing(dev);
pch_set_acpi_mode();
pch_fixups(dev);