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mb/google/fizz: Add AC/DC loadline settings 

This patch adds AC and DC loadline settings since vr_config_enable is
set. Without correct AD/DC loadline settings, VRs reported incorrect
VID values which caused CPU freqency clipping. The clipping reason
could be retrieved from MSR 0x64F. From VRTT report, the AC/DC
loadline resistances are within spec, we can use default value defined
in Table 6-1, doc #543977.

BUG=b:70646304
BRANCH=None
TEST=emerge-fizz coreboot chromeos-bootimage & Read AC/DC loadline
     settings from DCI to ensure the values were programmed correctly.

Change-Id: Id0ce29fa5726ca3711aa4c822fb123e2de7bc48f
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/23349
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Gaggery Tsai 2018-01-22 11:17:28 +08:00 committed by Stefan Reinauer
parent 94ef4a8a47
commit 63278ab07d
1 changed files with 10 additions and 0 deletions
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10
src/mainboard/google/fizz/devicetree.cb
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@ -116,6 +116,8 @@ chip soc/intel/skylake
#| ImonOffset | 0 | 0 | 0 | 0 | #| ImonOffset | 0 | 0 | 0 | 0 |
#| IccMax | 7A | 34A | 35A | 35A | #| IccMax | 7A | 34A | 35A | 35A |
#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
#| AcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m |
#| DcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m |
#+----------------+-------+-------+-------+-------+ #+----------------+-------+-------+-------+-------+
#Note: IccMax settings are moved to SoC code #Note: IccMax settings are moved to SoC code
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
@ -128,6 +130,8 @@ chip soc/intel/skylake
.imon_slope = 0x0, .imon_slope = 0x0,
.imon_offset = 0x0, .imon_offset = 0x0,
.voltage_limit = 1520, .voltage_limit = 1520,
.ac_loadline = 1030,
.dc_loadline = 1030,
}" }"
register "domain_vr_config[VR_IA_CORE]" = "{ register "domain_vr_config[VR_IA_CORE]" = "{
@ -140,6 +144,8 @@ chip soc/intel/skylake
.imon_slope = 0x0, .imon_slope = 0x0,
.imon_offset = 0x0, .imon_offset = 0x0,
.voltage_limit = 1520, .voltage_limit = 1520,
.ac_loadline = 240,
.dc_loadline = 240,
}" }"
register "domain_vr_config[VR_GT_UNSLICED]" = "{ register "domain_vr_config[VR_GT_UNSLICED]" = "{
@ -152,6 +158,8 @@ chip soc/intel/skylake
.imon_slope = 0x0, .imon_slope = 0x0,
.imon_offset = 0x0, .imon_offset = 0x0,
.voltage_limit = 1520, .voltage_limit = 1520,
.ac_loadline = 310,
.dc_loadline = 310,
}" }"
register "domain_vr_config[VR_GT_SLICED]" = "{ register "domain_vr_config[VR_GT_SLICED]" = "{
@ -164,6 +172,8 @@ chip soc/intel/skylake
.imon_slope = 0x0, .imon_slope = 0x0,
.imon_offset = 0x0, .imon_offset = 0x0,
.voltage_limit = 1520, .voltage_limit = 1520,
.ac_loadline = 310,
.dc_loadline = 310,
}" }"
# Enable Root port 3(x1) for LAN. # Enable Root port 3(x1) for LAN.