sc7180: Add SPI-NOR support
This implements the SPI-NOR driver for the Qualcomm QSPI core. Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/27483/58 Change-Id: I2eb8cf90aa4559541ba293b3fd2870896bed20b7 Signed-off-by: Akash Asthana <akashast@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35501 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Akash Asthana
Patrick Georgi
parent
7e51f15129
commit
634c783d1f
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@ -22,4 +22,13 @@ config VBOOT
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select VBOOT_MUST_REQUEST_DISPLAY
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select VBOOT_STARTS_IN_BOOTBLOCK
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config SC7180_QSPI
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bool
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default y if COMMON_CBFS_SPI_WRAPPER
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prompt "Build Flash Using SPI-NOR"
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config BOOT_DEVICE_SPI_FLASH_BUS
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int
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default 16
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endif
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@ -9,6 +9,7 @@ bootblock-y += spi.c
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bootblock-y += gpio.c
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bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c
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bootblock-y += clock.c
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bootblock-$(CONFIG_SC7180_QSPI) += qspi.c
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################################################################################
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verstage-y += timer.c
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@ -16,6 +17,7 @@ verstage-y += spi.c
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verstage-y += gpio.c
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verstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c
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verstage-y += clock.c
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verstage-$(CONFIG_SC7180_QSPI) += qspi.c
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################################################################################
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romstage-y += cbmem.c
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@ -28,6 +30,7 @@ romstage-y += spi.c
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romstage-y += gpio.c
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romstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c
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romstage-y += clock.c
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romstage-$(CONFIG_SC7180_QSPI) += qspi.c
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################################################################################
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ramstage-y += soc.c
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@ -36,6 +39,7 @@ ramstage-y += spi.c
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ramstage-y += gpio.c
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ramstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c
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ramstage-y += clock.c
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ramstage-$(CONFIG_SC7180_QSPI) += qspi.c
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################################################################################
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@ -16,9 +16,11 @@
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#include <bootblock_common.h>
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#include <soc/clock.h>
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#include <soc/mmu.h>
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#include <soc/qspi.h>
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void bootblock_soc_init(void)
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{
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sc7180_mmu_init();
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clock_init();
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quadspi_init(25 * MHz);
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}
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@ -0,0 +1,121 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2019 Qualcomm Technologies.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <types.h>
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#include <soc/addressmap.h>
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#include <spi-generic.h>
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#ifndef __SOC_QUALCOMM_SC7180_QSPI_H__
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#define __SOC_QUALCOMM_SC7180_QSPI_H__
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struct sc7180_qspi_regs {
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u32 mstr_cfg;
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u32 ahb_mstr_cfg;
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u32 reserve_0;
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u32 mstr_int_en;
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u32 mstr_int_sts;
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u32 pio_xfer_ctrl;
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u32 pio_xfer_cfg;
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u32 pio_xfer_sts;
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u32 pio_dataout_1byte;
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u32 pio_dataout_4byte;
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u32 rd_fifo_cfg;
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u32 rd_fifo_sts;
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u32 rd_fifo_rst;
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u32 reserve_1[3];
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u32 next_dma_desc_addr;
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u32 current_dma_desc_addr;
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u32 current_mem_addr;
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u32 hw_version;
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u32 rd_fifo[16];
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};
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check_member(sc7180_qspi_regs, rd_fifo, 0x50);
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static struct sc7180_qspi_regs * const sc7180_qspi = (void *) QSPI_BASE;
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// MSTR_CONFIG register
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#define TX_DATA_OE_DELAY_SHIFT 24
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#define TX_DATA_OE_DELAY_MASK (0x3 << TX_DATA_OE_DELAY_SHIFT)
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#define TX_CS_N_DELAY_SHIFT 22
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#define TX_CS_N_DELAY_MASK (0x3 << TX_CS_N_DELAY_SHIFT)
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#define TX_CLK_DELAY_SHIFT 20
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#define TX_CLK_DELAY_MASK (0x3 << TX_CLK_DELAY_SHIFT)
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#define TX_DATA_DELAY_SHIFT 18
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#define TX_DATA_DELAY_MASK (0x3 << TX_DATA_DELAY_SHIFT)
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#define LPA_BASE_SHIFT 14
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#define LPA_BASE_MASK (0xF << LPA_BASE_SHIFT)
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#define SBL_EN BIT(13)
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#define CHIP_SELECT_NUM BIT(12)
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#define SPI_MODE_SHIFT 10
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#define SPI_MODE_MASK (0x3 << SPI_MODE_SHIFT)
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#define BIG_ENDIAN_MODE BIT(9)
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#define DMA_ENABLE BIT(8)
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#define PIN_WPN BIT(7)
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#define PIN_HOLDN BIT(6)
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#define FB_CLK_EN BIT(4)
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#define FULL_CYCLE_MODE BIT(3)
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// MSTR_INT_ENABLE and MSTR_INT_STATUS register
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#define DMA_CHAIN_DONE BIT(31)
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#define TRANSACTION_DONE BIT(16)
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#define WRITE_FIFO_OVERRUN BIT(11)
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#define WRITE_FIFO_FULL BIT(10)
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#define HRESP_FROM_NOC_ERR BIT(3)
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#define RESP_FIFO_RDY BIT(2)
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#define RESP_FIFO_NOT_EMPTY BIT(1)
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#define RESP_FIFO_UNDERRUN BIT(0)
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// PIO_TRANSFER_CONFIG register
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#define TRANSFER_FRAGMENT BIT(8)
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#define MULTI_IO_MODE_SHIFT 1
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#define MULTI_IO_MODE_MASK (0x7 << MULTI_IO_MODE_SHIFT)
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#define TRANSFER_DIRECTION BIT(0)
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// PIO_TRANSFER_STATUS register
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#define WR_FIFO_BYTES_SHIFT 16
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#define WR_FIFO_BYTES_MASK (0xFFFF << WR_FIFO_BYTES_SHIFT)
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// RD_FIFO_CONFIG register
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#define CONTINUOUS_MODE BIT(0)
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// RD_FIFO_STATUS register
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#define FIFO_EMPTY BIT(11)
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#define WR_CNTS_SHIFT 4
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#define WR_CNTS_MASK (0x7F << WR_CNTS_SHIFT)
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#define RDY_64BYTE BIT(3)
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#define RDY_32BYTE BIT(2)
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#define RDY_16BYTE BIT(1)
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#define FIFO_RDY BIT(0)
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// RD_FIFO_RESET register
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#define RESET_FIFO BIT(0)
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#define QSPI_MAX_PACKET_COUNT 0xFFC0
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void quadspi_init(uint32_t hz);
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int sc7180_claim_bus(const struct spi_slave *slave);
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int sc7180_setup_bus(const struct spi_slave *slave);
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void sc7180_release_bus(const struct spi_slave *slave);
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int sc7180_xfer(const struct spi_slave *slave, const void *dout,
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size_t out_bytes, void *din, size_t in_bytes);
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int sc7180_xfer_dual(const struct spi_slave *slave, const void *dout,
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size_t out_bytes, void *din, size_t in_bytes);
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#endif /* __SOC_QUALCOMM_SC7180_QSPI_H__ */
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@ -0,0 +1,306 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <spi-generic.h>
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#include <spi_flash.h>
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#include <arch/cache.h>
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#include <device/mmio.h>
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#include <soc/addressmap.h>
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#include <soc/qspi.h>
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#include <soc/gpio.h>
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#include <soc/clock.h>
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#include <symbols.h>
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#include <assert.h>
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#include <gpio.h>
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#include <string.h>
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#define CACHE_LINE_SIZE 64
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static int curr_desc_idx = -1;
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struct cmd_desc {
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uint32_t data_address;
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uint32_t next_descriptor;
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uint32_t direction:1;
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uint32_t multi_io_mode:3;
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uint32_t reserved1:4;
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uint32_t fragment:1;
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uint32_t reserved2:7;
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uint32_t length:16;
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//------------------------//
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uint32_t bounce_src;
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uint32_t bounce_dst;
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uint32_t bounce_length;
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uint64_t padding[5];
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};
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enum qspi_mode {
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SDR_1BIT = 1,
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SDR_2BIT = 2,
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SDR_4BIT = 3,
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DDR_1BIT = 5,
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DDR_2BIT = 6,
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DDR_4BIT = 7,
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};
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enum cs_state {
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CS_DEASSERT,
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CS_ASSERT
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};
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struct xfer_cfg {
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enum qspi_mode mode;
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};
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enum bus_xfer_direction {
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MASTER_READ = 0,
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MASTER_WRITE = 1,
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};
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struct {
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struct cmd_desc descriptors[3];
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uint8_t buffers[3][CACHE_LINE_SIZE];
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} *dma = (void *)_dma_coherent;
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static void dma_transfer_chain(struct cmd_desc *chain)
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{
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uint32_t mstr_int_status;
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write32(&sc7180_qspi->mstr_int_sts, 0xFFFFFFFF);
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write32(&sc7180_qspi->next_dma_desc_addr, (uint32_t)(uintptr_t) chain);
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while (1) {
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mstr_int_status = read32(&sc7180_qspi->mstr_int_sts);
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if (mstr_int_status & DMA_CHAIN_DONE)
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break;
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}
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}
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static void flush_chain(void)
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{
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struct cmd_desc *desc = &dma->descriptors[0];
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uint8_t *src;
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uint8_t *dst;
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dma_transfer_chain(desc);
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while (desc) {
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if (desc->direction == MASTER_READ) {
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if (desc->bounce_length == 0)
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dcache_invalidate_by_mva(
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(void *)(uintptr_t) desc->data_address,
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desc->length);
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else {
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src = (void *)(uintptr_t) desc->bounce_src;
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dst = (void *)(uintptr_t) desc->bounce_dst;
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memcpy(dst, src, desc->bounce_length);
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}
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}
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desc = (void *)(uintptr_t) desc->next_descriptor;
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}
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curr_desc_idx = -1;
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}
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static struct cmd_desc *allocate_descriptor(void)
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{
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struct cmd_desc *current;
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struct cmd_desc *next;
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uint8_t index;
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current = (curr_desc_idx == -1) ?
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NULL : &dma->descriptors[curr_desc_idx];
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index = ++curr_desc_idx;
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next = &dma->descriptors[index];
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next->data_address = (uint32_t) (uintptr_t) dma->buffers[index];
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next->next_descriptor = 0;
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next->direction = MASTER_READ;
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next->multi_io_mode = 0;
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next->reserved1 = 0;
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next->fragment = 0;
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next->reserved2 = 0;
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next->length = 0;
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next->bounce_src = 0;
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next->bounce_dst = 0;
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next->bounce_length = 0;
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if (current) {
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current->next_descriptor = (uint32_t)(uintptr_t) next;
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current->fragment = 1;
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}
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return next;
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}
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static void cs_change(enum cs_state state)
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{
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gpio_set(GPIO(68), state == CS_DEASSERT);
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}
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static void configure_gpios(void)
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{
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gpio_output(GPIO(68), 1);
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gpio_configure(GPIO(64), GPIO64_FUNC_QSPI_DATA_0,
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GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_ENABLE);
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gpio_configure(GPIO(65), GPIO65_FUNC_QSPI_DATA_1,
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GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_ENABLE);
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gpio_configure(GPIO(63), GPIO63_FUNC_QSPI_CLK,
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GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_ENABLE);
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}
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static void queue_bounce_data(uint8_t *data, uint32_t data_bytes,
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enum qspi_mode data_mode, bool write)
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{
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struct cmd_desc *desc;
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uint8_t *ptr;
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desc = allocate_descriptor();
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desc->direction = write;
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desc->multi_io_mode = data_mode;
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ptr = (void *)(uintptr_t) desc->data_address;
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if (write) {
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memcpy(ptr, data, data_bytes);
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} else {
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desc->bounce_src = (uint32_t)(uintptr_t) ptr;
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desc->bounce_dst = (uint32_t)(uintptr_t) data;
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desc->bounce_length = data_bytes;
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}
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desc->length = data_bytes;
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}
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static void queue_direct_data(uint8_t *data, uint32_t data_bytes,
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enum qspi_mode data_mode, bool write)
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{
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struct cmd_desc *desc;
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desc = allocate_descriptor();
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desc->direction = write;
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desc->multi_io_mode = data_mode;
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desc->data_address = (uint32_t)(uintptr_t) data;
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desc->length = data_bytes;
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if (write)
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dcache_clean_by_mva(data, data_bytes);
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else
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dcache_invalidate_by_mva(data, data_bytes);
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}
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static void queue_data(uint8_t *data, uint32_t data_bytes,
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enum qspi_mode data_mode, bool write)
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{
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uint8_t *aligned_ptr;
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uint8_t *epilog_ptr;
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uint32_t prolog_bytes, aligned_bytes, epilog_bytes;
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if (data_bytes == 0)
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return;
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aligned_ptr =
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(uint8_t *)ALIGN_UP((uintptr_t)data, CACHE_LINE_SIZE);
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prolog_bytes = MIN(data_bytes, aligned_ptr - data);
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aligned_bytes = ALIGN_DOWN(data_bytes - prolog_bytes, CACHE_LINE_SIZE);
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epilog_bytes = data_bytes - prolog_bytes - aligned_bytes;
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epilog_ptr = data + prolog_bytes + aligned_bytes;
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if (prolog_bytes)
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queue_bounce_data(data, prolog_bytes, data_mode, write);
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if (aligned_bytes)
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queue_direct_data(aligned_ptr, aligned_bytes, data_mode, write);
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if (epilog_bytes)
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queue_bounce_data(epilog_ptr, epilog_bytes, data_mode, write);
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}
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static void reg_init(void)
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{
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uint32_t spi_mode;
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uint32_t tx_data_oe_delay, tx_data_delay;
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uint32_t mstr_config;
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spi_mode = 0;
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tx_data_oe_delay = 0;
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tx_data_delay = 0;
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mstr_config = (tx_data_oe_delay << TX_DATA_OE_DELAY_SHIFT) |
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(tx_data_delay << TX_DATA_DELAY_SHIFT) | (SBL_EN) |
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(spi_mode << SPI_MODE_SHIFT) |
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(PIN_HOLDN) |
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(FB_CLK_EN) |
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(DMA_ENABLE) |
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(FULL_CYCLE_MODE);
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write32(&sc7180_qspi->mstr_cfg, mstr_config);
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write32(&sc7180_qspi->ahb_mstr_cfg, 0xA42);
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write32(&sc7180_qspi->mstr_int_en, 0x0);
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write32(&sc7180_qspi->mstr_int_sts, 0xFFFFFFFF);
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write32(&sc7180_qspi->rd_fifo_cfg, 0x0);
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write32(&sc7180_qspi->rd_fifo_rst, RESET_FIFO);
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}
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void quadspi_init(uint32_t hz)
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{
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assert(dcache_line_bytes() == CACHE_LINE_SIZE);
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clock_configure_qspi(hz * 4);
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configure_gpios();
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reg_init();
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}
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int sc7180_claim_bus(const struct spi_slave *slave)
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{
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cs_change(CS_ASSERT);
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return 0;
|
||||
}
|
||||
|
||||
void sc7180_release_bus(const struct spi_slave *slave)
|
||||
{
|
||||
cs_change(CS_DEASSERT);
|
||||
}
|
||||
|
||||
static int xfer(enum qspi_mode mode, const void *dout, size_t out_bytes,
|
||||
void *din, size_t in_bytes)
|
||||
{
|
||||
if ((out_bytes && !dout) || (in_bytes && !din) ||
|
||||
(in_bytes && out_bytes)) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
queue_data((uint8_t *) (out_bytes ? dout : din),
|
||||
in_bytes | out_bytes, mode, !!out_bytes);
|
||||
|
||||
flush_chain();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int sc7180_xfer(const struct spi_slave *slave, const void *dout,
|
||||
size_t out_bytes, void *din, size_t in_bytes)
|
||||
{
|
||||
return xfer(SDR_1BIT, dout, out_bytes, din, in_bytes);
|
||||
}
|
||||
|
||||
int sc7180_xfer_dual(const struct spi_slave *slave, const void *dout,
|
||||
size_t out_bytes, void *din, size_t in_bytes)
|
||||
{
|
||||
return xfer(SDR_2BIT, dout, out_bytes, din, in_bytes);
|
||||
}
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2018, The Linux Foundation. All rights reserved.
|
||||
* Copyright (C) 2019, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
|
|
@ -15,12 +15,19 @@
|
|||
|
||||
#include <spi-generic.h>
|
||||
#include <spi_flash.h>
|
||||
#include <soc/qspi.h>
|
||||
|
||||
static const struct spi_ctrlr spi_ctrlr;
|
||||
static const struct spi_ctrlr qspi_ctrlr = {
|
||||
.claim_bus = sc7180_claim_bus,
|
||||
.release_bus = sc7180_release_bus,
|
||||
.xfer = sc7180_xfer,
|
||||
.xfer_dual = sc7180_xfer_dual,
|
||||
.max_xfer_size = QSPI_MAX_PACKET_COUNT,
|
||||
};
|
||||
|
||||
const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
|
||||
{
|
||||
.ctrlr = &spi_ctrlr,
|
||||
.ctrlr = &qspi_ctrlr,
|
||||
.bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS,
|
||||
.bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS,
|
||||
},
|
||||
|
|
|
|||
Loading…
Reference in New Issue