From 6362de3829c1762632e3aa16b1af0fd0a9a1e625 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 30 Jul 2020 11:31:55 +0530 Subject: [PATCH] soc/intel/{icl,jsl,tgl}: Remove SkipMpInit UPD as deprecated FSP default UPD for SkipMpInit is set to 0 which refers to run CPU feature programming on all cores (BSP + APs). Setting SkipMpInit=1 is not recommended as it will only limit CPU feature programming on BSP. TEST=Able to perform CPU feature programming by FSP on all cores using external MP PPI services. Change-Id: I22e70f5f15e53c5fabd78cc3698c4d718b607af6 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/44058 Tested-by: build bot (Jenkins) Reviewed-by: Wonkyu Kim --- src/soc/intel/icelake/fsp_params.c | 2 -- src/soc/intel/jasperlake/fsp_params.c | 6 +----- src/soc/intel/tigerlake/fsp_params.c | 6 +----- 3 files changed, 2 insertions(+), 12 deletions(-) diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index e3d355df86..d4485c6705 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -73,8 +73,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Mandatory to make use of CpuMpPpi implementation from ICL onwards */ params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); - /* TODO: Remove me as SkipMpInit is getting deprecated */ - params->SkipMpInit = 0; mainboard_silicon_init_params(params); diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index 204364bbd9..92ac5b8994 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -96,12 +96,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_dev_enabled(dev); /* Use coreboot MP PPI services if Kconfig is enabled */ - if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) { + if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); - params->SkipMpInit = 0; - } else { - params->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT); - } /* Chipset Lockdown */ if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 517d771705..a61a0255bc 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -104,12 +104,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_dev_enabled(dev); /* Use coreboot MP PPI services if Kconfig is enabled */ - if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) { + if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); - params->SkipMpInit = 0; - } else { - params->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT); - } /* D3Hot and D3Cold for TCSS */ params->D3HotEnable = !config->TcssD3HotDisable;