From 637f941f66441bb184d193eff3afe70702f0c1a5 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Mon, 6 Jul 2020 20:02:36 -0600 Subject: [PATCH] mb/google/zork: Update SPI mode to 100MHz, 1-2-2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change SPI speed from 66MHz, mode 1-1-2 to 100MHz mode 1-2-2. “1-2-2" means command, address and data are transmitted through 1 wire, 2 wire and 2 wire, respectively. BUG=b:160603142 TEST=Boot on trembyle, verify register settings. Signed-off-by: Martin Roth Change-Id: I14f96e3c085126c70e64ef3a3f5b7b54ce6cbffe Reviewed-on: https://review.coreboot.org/c/coreboot/+/43306 Reviewed-by: Felix Held Reviewed-by: Rob Barnes Tested-by: build bot (Jenkins) --- src/mainboard/google/zork/variants/baseboard/devicetree.cb | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree.cb b/src/mainboard/google/zork/variants/baseboard/devicetree.cb index 9db0d239d6..ca33bbd4bd 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree.cb @@ -140,11 +140,11 @@ chip soc/amd/picasso # SPI Configuration register "common_config.spi_config" = "{ - .normal_speed = SPI_SPEED_66M, /* MHz */ - .fast_speed = SPI_SPEED_66M, /* MHz */ + .normal_speed = SPI_SPEED_100M, /* MHz */ + .fast_speed = SPI_SPEED_100M, /* MHz */ .altio_speed = SPI_SPEED_66M, /* MHz */ .tpm_speed = SPI_SPEED_66M, /* MHz */ - .read_mode = SPI_READ_MODE_DUAL112, + .read_mode = SPI_READ_MODE_DUAL122, }" # eSPI Configuration