nb/intel/x4x/raminit: Support programming initials DD3 DLL setting
Adapt the programming of initial DLL values for DDR3. Change-Id: I67e48b4ae6f2076399133ba7b98ab1dfc0e0ab08 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Arthur Heymans
Patrick Georgi
parent
66a0f55c2e
commit
638240e98b
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@ -583,7 +583,8 @@ static void program_timings(struct sysinfo *s)
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MCHBAR16(0x400*i + 0x25b) = ((s->selected_timings.tRP + trpmod) << 9) |
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s->selected_timings.tRFC;
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MCHBAR16(0x400*i + 0x260) = (MCHBAR16(0x400*i + 0x260) & ~0x3fe) | (100 << 1);
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MCHBAR16(0x400*i + 0x260) = (MCHBAR16(0x400*i + 0x260) & ~0x3fe)
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| ((s->spd_type == DDR2 ? 100 : 256) << 1);
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MCHBAR8(0x400*i + 0x264) = 0xff;
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MCHBAR8(0x400*i + 0x25d) = (MCHBAR8(0x400*i + 0x25d) & ~0x3f) |
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s->selected_timings.tRAS;
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@ -636,18 +637,32 @@ static void program_timings(struct sysinfo *s)
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MCHBAR8(0x400*i + 0x24c) = MCHBAR8(0x400*i + 0x24c) & ~0x3;
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reg16 = 0;
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switch (s->selected_timings.mem_clk) {
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default:
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case MEM_CLOCK_667MHz:
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reg16 = 0x99;
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break;
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case MEM_CLOCK_800MHz:
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if (s->selected_timings.CAS == 5)
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reg16 = 0x19a;
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else if (s->selected_timings.CAS == 6)
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reg16 = 0x9a;
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break;
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if (s->spd_type == DDR2) {
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switch (s->selected_timings.mem_clk) {
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default:
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case MEM_CLOCK_667MHz:
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reg16 = 0x99;
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break;
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case MEM_CLOCK_800MHz:
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if (s->selected_timings.CAS == 5)
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reg16 = 0x19a;
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else if (s->selected_timings.CAS == 6)
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reg16 = 0x9a;
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break;
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}
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} else { /* DDR3 */
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switch (s->selected_timings.mem_clk) {
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default:
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case MEM_CLOCK_800MHz:
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case MEM_CLOCK_1066MHz:
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reg16 = 1;
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break;
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case MEM_CLOCK_1333MHz:
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reg16 = 2;
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break;
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}
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}
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reg16 &= 0x7;
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reg16 += twl + 9;
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reg16 <<= 10;
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@ -683,6 +698,14 @@ static void program_timings(struct sysinfo *s)
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MCHBAR8(0x12d) = (MCHBAR8(0x12d) & ~0xf) | reg8;
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MCHBAR8(0x12f) = 0x4c;
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reg32 = (1 << 31) | (0x80 << 14) | (1 << 13) | (0xa << 9);
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if (s->spd_type == DDR3) {
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MCHBAR8(0x114) = 0x42;
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reg16 = (512 - MAX(5, s->selected_timings.tRFC + 10000
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/ ddr2ps[s->selected_timings.mem_clk]))
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/ 2;
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reg16 &= 0x1ff;
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reg32 = (reg16 << 22) | (0x80 << 14) | (0xa << 9);
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}
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MCHBAR32(0x6c0) = (MCHBAR32(0x6c0) & ~0xffffff00) | reg32;
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MCHBAR8(0x6c4) = (MCHBAR8(0x6c4) & ~0x7) | 0x2;
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}
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@ -693,6 +716,9 @@ static void program_dll(struct sysinfo *s)
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u16 reg16 = 0;
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u32 reg32 = 0;
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const u8 rank2clken[8] = { 0x04, 0x01, 0x20, 0x08, 0x01, 0x04,
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0x08, 0x10 };
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MCHBAR16(0x180) = (MCHBAR16(0x180) & ~0x7e06) | 0xc04;
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MCHBAR16(0x182) = (MCHBAR16(0x182) & ~0x3ff) | 0xc8;
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MCHBAR16(0x18a) = (MCHBAR16(0x18a) & ~0x1f1f) | 0x0f0f;
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@ -701,11 +727,15 @@ static void program_dll(struct sysinfo *s)
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switch (s->selected_timings.mem_clk) {
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default:
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case MEM_CLOCK_667MHz:
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case MEM_CLOCK_1333MHz:
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reg16 = (0xa << 9) | 0xa;
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break;
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case MEM_CLOCK_800MHz:
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reg16 = (0x9 << 9) | 0x9;
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break;
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case MEM_CLOCK_1066MHz:
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reg16 = (0x7 << 9) | 0x7;
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break;
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}
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MCHBAR16(0x19c) = (MCHBAR16(0x19c) & ~0x1e0f) | reg16;
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MCHBAR16(0x19c) = (MCHBAR16(0x19c) & ~0x2030) | 0x2010;
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@ -729,14 +759,27 @@ static void program_dll(struct sysinfo *s)
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udelay(1); // 533ns
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// ME related
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MCHBAR32(0x1a0) = (MCHBAR32(0x1a0) & ~0x7ffffff) | 0x551803;
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MCHBAR32(0x1a0) = (MCHBAR32(0x1a0) & ~0x7ffffff)
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| (s->spd_type == DDR2 ? 0x551803 : 0x555801);
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MCHBAR16(0x1b4) = MCHBAR16(0x1b4) & ~0x800;
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MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 0xf0;
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if (s->spd_type == DDR2) {
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MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 0xf0;
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} else { /* DDR3 */
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reg8 = 0x9; /* 0x9 << 4 ?? */
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if (s->dimms[0].ranks == 2)
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reg8 &= ~0x80;
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if (s->dimms[3].ranks == 2)
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reg8 &= ~0x10;
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MCHBAR8(0x1a8) = (MCHBAR8(0x1a8) & ~0xf0) | reg8;
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}
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FOR_EACH_CHANNEL(i) {
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reg16 = 0;
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MCHBAR16(0x400*i + 0x59c) = MCHBAR16(0x400*i + 0x59c) & ~0x3000;
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if ((s->spd_type == DDR3) && (i == 0))
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reg16 = (0x3 << 12);
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MCHBAR16(0x400*i + 0x59c) = (MCHBAR16(0x400*i + 0x59c)
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& ~0x3000) | reg16;
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reg32 = 0;
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FOR_EACH_RANK_IN_CHANNEL(r) {
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@ -747,30 +790,50 @@ static void program_dll(struct sysinfo *s)
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MCHBAR32(0x400*i + 0x59c) = (MCHBAR32(0x400*i + 0x59c) & ~0xfff) | reg32;
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MCHBAR8(0x400*i + 0x594) = MCHBAR8(0x400*i + 0x594) & ~1;
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if (!CHANNEL_IS_POPULATED(s->dimms, i)) {
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printk(BIOS_DEBUG, "No dimms in channel %d\n", i);
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reg8 = 0x3f;
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} else if (ONLY_DIMMA_IS_POPULATED(s->dimms, i)) {
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printk(BIOS_DEBUG, "DimmA populated only in channel %d\n", i);
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reg8 = 0x38;
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} else if (ONLY_DIMMB_IS_POPULATED(s->dimms, i)) {
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printk(BIOS_DEBUG, "DimmB populated only in channel %d\n", i);
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reg8 = 0x7;
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} else if (BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) {
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printk(BIOS_DEBUG, "Both dimms populated in channel %d\n", i);
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reg8 = 0;
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} else {
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die("Unhandled case\n");
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if (s->spd_type == DDR2) {
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if (!CHANNEL_IS_POPULATED(s->dimms, i)) {
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printk(BIOS_DEBUG,
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"No dimms in channel %d\n", i);
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reg8 = 0x3f;
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} else if (ONLY_DIMMA_IS_POPULATED(s->dimms, i)) {
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printk(BIOS_DEBUG,
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"DimmA populated only in channel %d\n",
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i);
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reg8 = 0x38;
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} else if (ONLY_DIMMB_IS_POPULATED(s->dimms, i)) {
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printk(BIOS_DEBUG,
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"DimmB populated only in channel %d\n",
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i);
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reg8 = 0x7;
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} else if (BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) {
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printk(BIOS_DEBUG,
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"Both dimms populated in channel %d\n",
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i);
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reg8 = 0;
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} else {
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die("Unhandled case\n");
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}
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MCHBAR32(0x400*i + 0x5a0) = (MCHBAR32(0x400*i + 0x5a0)
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& ~0x3f000000) | ((u32)(reg8 << 24));
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} else { /* DDR3 */
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FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, i, r) {
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MCHBAR8(0x400 * i + 0x5a0 + 3) =
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MCHBAR8(0x400 * i + 0x5a0 + 3)
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& ~rank2clken[r + i * 4];
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}
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}
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//reg8 = 0x00; // FIXME don't switch on all clocks anyway
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MCHBAR32(0x400*i + 0x5a0) = (MCHBAR32(0x400*i + 0x5a0) & ~0x3f000000) |
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((u32)(reg8 << 24));
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} // END EACH CHANNEL
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MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 1;
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MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x4;
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if (s->spd_type == DDR2) {
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MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 1;
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MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x4;
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} else { /* DDR3 */
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MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~1;
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MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 0x4;
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}
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// Update DLL timing
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MCHBAR8(0x1a4) = MCHBAR8(0x1a4) & ~0x80;
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@ -780,17 +843,33 @@ static void program_dll(struct sysinfo *s)
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FOR_EACH_POPULATED_CHANNEL(s->dimms, i) {
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MCHBAR16(0x400*i + 0x5f0) = (MCHBAR16(0x400*i + 0x5f0) & ~0x3fc) | 0x3fc;
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MCHBAR32(0x400*i + 0x5fc) = MCHBAR32(0x400*i + 0x5fc) & ~0xcccccccc;
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MCHBAR8(0x400*i + 0x5d9) = (MCHBAR8(0x400*i + 0x5d9) & ~0xf0) | 0x70;
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MCHBAR16(0x400*i + 0x590) = (MCHBAR16(0x400*i + 0x590) & ~0xffff) | 0x5555;
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MCHBAR8(0x400*i + 0x5d9) = (MCHBAR8(0x400*i + 0x5d9) & ~0xf0)
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| (s->spd_type == DDR2 ? 0x70 : 0x60);
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MCHBAR16(0x400*i + 0x590) = (MCHBAR16(0x400*i + 0x590) & ~0xffff)
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| (s->spd_type == DDR2 ? 0x5555 : 0xa955);
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}
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FOR_EACH_POPULATED_CHANNEL(s->dimms, i) {
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const struct dll_setting *setting;
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if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz)
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switch(s->selected_timings.mem_clk) {
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default: /* Should not happen */
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case MEM_CLOCK_667MHz:
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setting = default_ddr2_667_ctrl;
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else
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setting = default_ddr2_800_ctrl;
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break;
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case MEM_CLOCK_800MHz:
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if (s->spd_type == DDR2)
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setting = default_ddr2_800_ctrl;
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else
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setting = default_ddr3_800_ctrl[s->nmode - 1];
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break;
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case MEM_CLOCK_1066MHz:
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setting = default_ddr3_1067_ctrl[s->nmode - 1];
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break;
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case MEM_CLOCK_1333MHz:
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setting = default_ddr3_1333_ctrl[s->nmode - 1];
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break;
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}
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clkset0(i, &setting[CLKSET0]);
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clkset1(i, &setting[CLKSET1]);
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@ -863,24 +942,42 @@ static void program_dll(struct sysinfo *s)
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async = 1;
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}
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clk = 0x1a;
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if (async != 1) {
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reg8 = MCHBAR8(0x188) & 0x1e;
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if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz &&
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s->selected_timings.fsb_clk == FSB_CLOCK_800MHz) {
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clk = 0x10;
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} else if (s->selected_timings.mem_clk == MEM_CLOCK_800MHz) {
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clk = 0x10;
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} else {
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clk = 0x1a;
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switch (s->selected_timings.mem_clk) {
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case MEM_CLOCK_667MHz:
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clk = 0x1a;
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if (async != 1) {
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if (s->selected_timings.fsb_clk == FSB_CLOCK_800MHz)
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clk = 0x10;
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}
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break;
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case MEM_CLOCK_800MHz:
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case MEM_CLOCK_1066MHz:
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if (async != 1)
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clk = 0x10;
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else
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clk = 0x1a;
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break;
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case MEM_CLOCK_1333MHz:
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clk = 0x18;
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break;
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default:
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clk = 0x1a;
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break;
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}
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if (async != 1)
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reg8 = MCHBAR8(0x188) & 0x1e;
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MCHBAR8(0x180) = MCHBAR8(0x180) & ~0x80;
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if ((s->selected_timings.fsb_clk == FSB_CLOCK_800MHz) &&
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(s->selected_timings.mem_clk == MEM_CLOCK_667MHz)) {
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if ((s->spd_type == DDR3 && s->selected_timings.mem_clk == MEM_CLOCK_1066MHz)
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|| (s->spd_type == DDR2 && s->selected_timings.fsb_clk == FSB_CLOCK_800MHz
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&& s->selected_timings.mem_clk == MEM_CLOCK_667MHz)) {
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i = MCHBAR8(0x1c8) & 0xf;
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i = (i + 10) % 14;
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if (s->spd_type == DDR2)
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i = (i + 10) % 14;
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else /* DDR3 */
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i = (i + 3) % 12;
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MCHBAR8(0x1c8) = (MCHBAR8(0x1c8) & ~0x1f) | i;
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MCHBAR8(0x180) = MCHBAR8(0x180) | 0x10;
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while (MCHBAR8(0x180) & 0x10)
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@ -926,18 +1023,33 @@ static void select_default_dq_dqs_settings(struct sysinfo *s)
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s->rt_dqs[ch][lane].tap = 7;
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s->rt_dqs[ch][lane].pi = 0;
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} else { /* DDR3 */
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/* TODO: DDR3 write DQ-DQS */
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memcpy(s->dqs_settings[ch],
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default_ddr3_800_dqs[s->nmode - 1],
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sizeof(s->dqs_settings[ch]));
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memcpy(s->dq_settings[ch],
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default_ddr3_800_dq[s->nmode - 1],
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sizeof(s->dq_settings[ch]));
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s->rt_dqs[ch][lane].tap = 6;
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s->rt_dqs[ch][lane].pi = 2;
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s->rt_dqs[ch][lane].pi = 3;
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}
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break;
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case MEM_CLOCK_1066MHz:
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/* TODO: DDR3 write DQ-DQS */
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memcpy(s->dqs_settings[ch],
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default_ddr3_1067_dqs[s->nmode - 1],
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sizeof(s->dqs_settings[ch]));
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memcpy(s->dq_settings[ch],
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default_ddr3_1067_dq[s->nmode - 1],
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sizeof(s->dq_settings[ch]));
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s->rt_dqs[ch][lane].tap = 5;
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s->rt_dqs[ch][lane].pi = 2;
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s->rt_dqs[ch][lane].pi = 3;
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break;
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case MEM_CLOCK_1333MHz:
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/* TODO: DDR3 write DQ-DQS */
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memcpy(s->dqs_settings[ch],
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default_ddr3_1333_dqs[s->nmode - 1],
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sizeof(s->dqs_settings[ch]));
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memcpy(s->dq_settings[ch],
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default_ddr3_1333_dq[s->nmode - 1],
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sizeof(s->dq_settings[ch]));
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s->rt_dqs[ch][lane].tap = 7;
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s->rt_dqs[ch][lane].pi = 0;
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break;
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