From 6386cc99736dd7501faeb332d9c231ec685bf898 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 12 Jul 2021 10:53:25 +0200 Subject: [PATCH] mb/siemens/chili: Drop ineffective `SaGv` setting SaGv is only available on ULT/ULX processors, which use PCH-LP. Given that the Siemens Chili board selects `SOC_INTEL_CANNONLAKE_PCH_H`, it does not use ULT/ULX processors, and thus does not support SaGv. Drop the `SaGv` setting from the devicetrees, as it has no effect. Change-Id: I5be518cce08206ad149efd1665e44a7111b24202 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/56205 Reviewed-by: Felix Singer Tested-by: build bot (Jenkins) --- src/mainboard/siemens/chili/variants/base/devicetree.cb | 1 - src/mainboard/siemens/chili/variants/chili/devicetree.cb | 1 - 2 files changed, 2 deletions(-) diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb index 52d8f1ca6a..e49ccd7c78 100644 --- a/src/mainboard/siemens/chili/variants/base/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb @@ -2,7 +2,6 @@ chip soc/intel/cannonlake # FSP configuration - register "SaGv" = "SaGv_Enabled" register "RMT" = "0" register "PchHdaDspEnable" = "0" diff --git a/src/mainboard/siemens/chili/variants/chili/devicetree.cb b/src/mainboard/siemens/chili/variants/chili/devicetree.cb index 37a33e7833..f22e42ca79 100644 --- a/src/mainboard/siemens/chili/variants/chili/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/chili/devicetree.cb @@ -2,7 +2,6 @@ chip soc/intel/cannonlake # FSP configuration - register "SaGv" = "SaGv_Enabled" register "RMT" = "0" register "PchHdaDspEnable" = "0"