soc/intel/denverton_ns: Fix missing tsc_freq_mhz()

It was relying on bad weak implementation for postcar
and verstage.

Change-Id: I5a520e0166198c0565349c164f143f4a43649861
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Guckian
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com>

src/soc/intel/denverton_ns/Makefile.inc

@@ -31,6 +31,7 @@ bootblock-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c
 
 postcar-y += memmap.c
 postcar-y += spi.c
+postcar-y += tsc_freq.c
 postcar-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c
 
 romstage-y += memmap.c
@@ -80,6 +81,7 @@ smm-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c
 verstage-y += memmap.c
 verstage-y += reset.c
 verstage-y += spi.c
+verstage-y += tsc_freq.c
 verstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c
 
 CPPFLAGS_common += -I$(src)/soc/intel/denverton_ns/include