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nb/intel/gm45: Make polling loops more explicit 

Replace `while (...);` with `do {} while (...);` so that it's easier to
distinguish polling loops from something else, like function calls. The
`{}` can be understood as "nothing", so that the construct is naturally
read as "do nothing while (...)".

Another reason to prefer this method is that Jenkins does not complain.

Change-Id: Ifbf3cf072f8b817b2fdeece4ef89bae0822bb6e6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Angel Pons 2022-11-02 01:04:24 +01:00 committed by Eric Lai
parent 5faaca09b8
commit 6397687940
1 changed files with 3 additions and 3 deletions
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6
src/northbridge/intel/gm45/pcie.c
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@ -33,12 +33,12 @@ static void init_egress(void)
epbar_write32(EP_PORTARB(7), 0x00005555);
epbar_setbits32(EPVC1RCTL, 1 << 16);
while ((epbar_read8(EPVC1RSTS) & 1) != 0);
do {} while ((epbar_read8(EPVC1RSTS) & 1) != 0);
/* VC1: enable */
epbar_setbits32(EPVC1RCTL, 1 << 31);
while ((epbar_read8(EPVC1RSTS) & 2) != 0);
do {} while ((epbar_read8(EPVC1RSTS) & 2) != 0);
}
/* MCH side */
@ -56,7 +56,7 @@ static void init_dmi(int b2step)
/* VC1: enable */
dmibar_setbits32(DMIVC1RCTL, 1 << 31);
while ((dmibar_read8(DMIVC1RSTS) & VC1NP) != 0);
do {} while ((dmibar_read8(DMIVC1RSTS) & VC1NP) != 0);
/* additional configuration. */
dmibar_setbits32(0x200, 3 << 13);