soc/intel/baytrail,braswell: Sync PCI memory region in ASL

Baytrail had (only) occurence of DwordMemory vs DWordMemory.
Braswell one had bogus comments about the PCI memory range.

The actual region details are dynamically filled in _CRS.

Change-Id: I8d1bf45c6e5520c0b7643602843c665bfb81f9da
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki 2021-02-01 13:57:45 +02:00
parent 00b5f53361
commit 639cc9c6ba
2 changed files with 4 additions and 4 deletions

View File

@ -143,7 +143,7 @@ Name (MCRS, ResourceTemplate()
0x00000000,,, LMEM) 0x00000000,,, LMEM)
/* PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) */ /* PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) */
DwordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite, Cacheable, ReadWrite,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000,,, PMEM) 0x00000000,,, PMEM)

View File

@ -144,11 +144,11 @@ Method (_CRS, 0, Serialized)
0x00000000, 0x20000000, 0x201FFFFF, 0x00000000, 0x00000000, 0x20000000, 0x201FFFFF, 0x00000000,
0x00200000,,, LMEM) 0x00200000,,, LMEM)
/* PCI Memory Region (Top of memory-0xfeafffff) */ /* PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite, Cacheable, ReadWrite,
0x00000000, 0xfea00000, 0xfeafffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00100000,,, PMEM) 0x00000000,,, PMEM)
/* TPM Area (0xfed40000-0xfed44fff) */ /* TPM Area (0xfed40000-0xfed44fff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,