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soc/intel/skylake: Drop unreferenced PttSwitch dt setting 

The value for this setting is not used anywhere. Drop it.

Change-Id: I75f6cdec6c69b374a07519bf9058b8f6e4916307
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Angel Pons 2020-12-11 16:55:04 +01:00
parent 056c3a9ff2
commit 63a078e66d
14 changed files with 0 additions and 15 deletions
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1
src/mainboard/51nb/x210/devicetree.cb
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@ -47,7 +47,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "0"
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "1"
register "SaGv" = "SaGv_Enabled"

1
src/mainboard/google/eve/devicetree.cb
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@ -43,7 +43,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "3"

1
src/mainboard/google/fizz/variants/baseboard/devicetree.cb
View File

@ -74,7 +74,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "3"

1
src/mainboard/google/glados/devicetree.cb
View File

@ -42,7 +42,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "3"

1
src/mainboard/google/poppy/variants/atlas/devicetree.cb
View File

@ -49,7 +49,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "3"

1
src/mainboard/google/poppy/variants/baseboard/devicetree.cb
View File

@ -39,7 +39,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "3"

1
src/mainboard/google/poppy/variants/nami/devicetree.cb
View File

@ -38,7 +38,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "3"

1
src/mainboard/google/poppy/variants/nautilus/devicetree.cb
View File

@ -39,7 +39,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "3"

1
src/mainboard/google/poppy/variants/nocturne/devicetree.cb
View File

@ -44,7 +44,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "3"

1
src/mainboard/google/poppy/variants/rammus/devicetree.cb
View File

@ -49,7 +49,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "3"

1
src/mainboard/google/poppy/variants/soraka/devicetree.cb
View File

@ -39,7 +39,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "3"

1
src/mainboard/purism/librem_skl/devicetree.cb
View File

@ -53,7 +53,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "0"
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "3"

1
src/mainboard/razer/blade_stealth_kbl/devicetree.cb
View File

@ -33,7 +33,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "0"
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "1"
register "SaGv" = "SaGv_Enabled"

2
src/soc/intel/skylake/chip.h
View File

@ -299,8 +299,6 @@ struct soc_intel_skylake_config {
u8 ScsEmmcHs400RxStrobeDll1;
u8 ScsEmmcHs400TxDataDll;
u8 PttSwitch;
enum {
Display_iGFX,
Display_PEG,