mb/google/brya/acpi/power: Clean up ASL code
Mostly there are too many extraneous `\_SB.PCI0.` prefixes, also a few minor cleanups, but nothing functional. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I79d919d2f04f57232f8f6a4e4d0690833faeb834 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
This commit is contained in:
Tim Wawrzynczak
Felix Held
parent
7bc8fd58a3
commit
63aca9233b
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@ -27,6 +27,9 @@ External (\_SB.PCI0.PMC.IPCS, MethodObj)
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#define SRCCLK_DISABLE 0
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#define SRCCLK_ENABLE 1
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#define GPU_POWER_STATE_OFF 0
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#define GPU_POWER_STATE_ON 1
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/*
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* For board revs 3 and later, the PG pin for the NVVDD VR moved from
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* GPP_E16 to GPP_E3. To accommodate this, this DSDT contains a Name
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@ -52,8 +55,6 @@ Name (OPS0, OPTIMUS_CONTROL_NO_RUN_PS0)
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Name (GC6E, GC6_STATE_EXITED)
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/* Power State, GCOFF, GCON */
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#define GPU_POWER_STATE_OFF 0
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#define GPU_POWER_STATE_ON 1
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Name (GPPS, GPU_POWER_STATE_ON)
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/* Defer GC6 entry / exit until D3-cold request */
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@ -108,29 +109,28 @@ Method (GC6I, 0, Serialized)
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GPPL (GPIO_GPU_NVVDD_EN, 0, 20)
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/* Deassert PG_GPU_ALLRAILS */
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\_SB.PCI0.CTXS (GPIO_GPU_ALLRAILS_PG)
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CTXS (GPIO_GPU_ALLRAILS_PG)
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/* Ramp down PEXVDD */
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\_SB.PCI0.CTXS (GPIO_PEXVDD_PWR_EN)
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CTXS (GPIO_PEXVDD_PWR_EN)
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GPPL (GPIO_PEXVDD_PG, 0, 20)
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Sleep (10)
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/* Deassert EN_PPVAR_GPU_NVVDD */
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\_SB.PCI0.CTXS (GPIO_NVVDD_PWR_EN)
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CTXS (GPIO_NVVDD_PWR_EN)
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GPPL (NVPG, 0, 20)
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Sleep (2)
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/* Assert GPU_PERST_L */
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\_SB.PCI0.CTXS (GPIO_GPU_PERST_L)
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CTXS (GPIO_GPU_PERST_L)
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/* Disable PCIe SRCCLK# */
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SRCC (SRCCLK_DISABLE)
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Printf ("dGPU entered GC6")
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GC6E = GC6_STATE_ENTERED
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}
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/* "GC6 Out", i.e. GC6 Exit Sequence */
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/* "GC6 Out", i.e. GC6 Exit Sequence */
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Method (GC6O, 0, Serialized)
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{
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GC6E = GC6_STATE_TRANSITION
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@ -139,26 +139,25 @@ Method (GC6O, 0, Serialized)
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SRCC (SRCCLK_ENABLE)
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/* Deassert GPU_PERST_L */
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\_SB.PCI0.STXS (GPIO_GPU_PERST_L)
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STXS (GPIO_GPU_PERST_L)
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/* Wait for GPU to assert GPU_NVVDD_EN */
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GPPL (GPIO_GPU_NVVDD_EN, 1, 20)
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/* Ramp up NVVDD */
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\_SB.PCI0.STXS (GPIO_NVVDD_PWR_EN)
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STXS (GPIO_NVVDD_PWR_EN)
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GPPL (NVPG, 1, 4)
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/* Ramp up PEXVDD */
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\_SB.PCI0.STXS (GPIO_PEXVDD_PWR_EN)
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GPPL (GPIO_PEXVDD_PG, 1, 4)
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STXS (GPIO_PEXVDD_PWR_EN)
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GPPL (GPIO_PEXVDD_PG, 1, 4)
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/* Assert PG_GPU_ALLRAILS */
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\_SB.PCI0.STXS (GPIO_GPU_ALLRAILS_PG)
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STXS (GPIO_GPU_ALLRAILS_PG)
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/* Put PCIe link into L0 state */
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/* Restore PCIe link back to L0 state */
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\_SB.PCI0.PEG0.LD23 ()
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Printf ("dGPU exited GC6")
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/* Wait for dGPU to reappear on the bus */
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Local0 = 50
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While (NVID != PCI_VID_NVIDIA)
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@ -198,38 +197,38 @@ Method (PGON, 0, Serialized)
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}
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/* Assert PERST# */
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\_SB.PCI0.CTXS (GPIO_GPU_PERST_L)
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CTXS (GPIO_GPU_PERST_L)
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/* Ramp up 1.8V rail */
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\_SB.PCI0.STXS (GPIO_1V8_PWR_EN)
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STXS (GPIO_1V8_PWR_EN)
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GPPL (GPIO_1V8_PG, 1, 20)
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/* Ramp up NV33 rail */
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\_SB.PCI0.STXS (GPIO_NV33_PWR_EN)
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STXS (GPIO_NV33_PWR_EN)
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GPPL (GPIO_NV33_PG, 1, 20)
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/* Ramp up NVVDD rail */
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\_SB.PCI0.STXS (GPIO_NVVDD_PWR_EN)
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STXS (GPIO_NVVDD_PWR_EN)
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GPPL (NVPG, 1, 5)
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/* Ramp up PEXVDD rail */
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\_SB.PCI0.STXS (GPIO_PEXVDD_PWR_EN)
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STXS (GPIO_PEXVDD_PWR_EN)
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GPPL (GPIO_PEXVDD_PG, 1, 5)
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/* Ramp up FBVDD rail (active low) */
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\_SB.PCI0.CTXS (GPIO_FBVDD_PWR_EN)
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CTXS (GPIO_FBVDD_PWR_EN)
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GPPL (GPIO_FBVDD_PG, 1, 5)
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/* All rails are good */
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\_SB.PCI0.STXS (GPIO_GPU_ALLRAILS_PG)
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STXS (GPIO_GPU_ALLRAILS_PG)
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Sleep (1)
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/* Deassert PERST# */
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\_SB.PCI0.STXS (GPIO_GPU_PERST_L)
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STXS (GPIO_GPU_PERST_L)
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GC6E = GC6_STATE_EXITED
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GPPS = GPU_POWER_STATE_ON
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Printf ("GPU Sequenced on")
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}
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/* GCOFF entry sequence */
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@ -242,47 +241,89 @@ Method (PGOF, 0, Serialized)
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}
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/* Assert PERST# */
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\_SB.PCI0.CTXS (GPIO_GPU_PERST_L)
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CTXS (GPIO_GPU_PERST_L)
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/* All rails are about to go down */
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\_SB.PCI0.CTXS (GPIO_GPU_ALLRAILS_PG)
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CTXS (GPIO_GPU_ALLRAILS_PG)
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Sleep (1)
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/* Ramp down FBVDD (active-low) and let rail discharge to <10% */
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\_SB.PCI0.STXS (GPIO_FBVDD_PWR_EN)
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STXS (GPIO_FBVDD_PWR_EN)
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GPPL (GPIO_FBVDD_PG, 0, 20)
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/* Ramp down PEXVDD and let rail discharge to <10% */
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\_SB.PCI0.CTXS (GPIO_PEXVDD_PWR_EN)
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CTXS (GPIO_PEXVDD_PWR_EN)
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GPPL (GPIO_PEXVDD_PG, 0, 20)
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Sleep (10)
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/* Ramp down NVVDD and let rail discharge to <10% */
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\_SB.PCI0.CTXS (GPIO_NVVDD_PWR_EN)
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CTXS (GPIO_NVVDD_PWR_EN)
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GPPL (NVPG, 0, 20)
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Sleep (2)
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/* Ramp down NV33 and let rail discharge to <10% */
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\_SB.PCI0.CTXS (GPIO_NV33_PWR_EN)
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CTXS (GPIO_NV33_PWR_EN)
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GPPL (GPIO_NV33_PG, 0, 20)
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Sleep (4)
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/* Ramp down 1.8V */
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\_SB.PCI0.CTXS (GPIO_1V8_PWR_EN)
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CTXS (GPIO_1V8_PWR_EN)
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GPPL (GPIO_1V8_PG, 0, 20)
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GCOT = Timer
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GPPS = GPU_POWER_STATE_OFF
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Printf ("GPU sequenced off")
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}
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/* GCOFF Out, i.e. full power-on sequence */
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Method (GCOO, 0, Serialized)
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{
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SRCC (SRCCLK_ENABLE)
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PGON ()
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\_SB.PCI0.PEG0.LD23 ()
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/* Wait for dGPU to reappear on the bus */
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Local0 = 50
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While (NVID != PCI_VID_NVIDIA)
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{
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Stall (100)
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Local0--
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If (Local0 == 0)
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{
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Break
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}
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}
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/* Restore the PEG LTR enable bit */
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LREN = SLTR
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/* Clear recoverable errors detected bit */
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CEDR = 1
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/* Restore the PEG LTR enable bit */
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LREN = SLTR
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/* Clear recoverable errors detected bit */
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CEDR = 1
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}
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/* GCOFF In, i.e. full power-off sequence */
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Method (GCOI, 0, Serialized)
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{
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/* Save the PEG port's LTR setting */
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SLTR = LREN
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\_SB.PCI0.PEG0.DL23 ()
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PGOF ()
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SRCC (SRCCLK_DISABLE)
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}
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/* Handle deferred GC6 vs. poweron request */
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Method (NPON, 0, Serialized)
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{
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If (DFEN == GC6_DEFER_ENABLE) /* 1 */
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If (DFEN == GC6_DEFER_ENABLE)
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{
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If (DFCO == GC6_DEFER_TYPE_EXIT_GC6) /* 3 */
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If (DFCO == GC6_DEFER_TYPE_EXIT_GC6)
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{
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GC6O ()
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}
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@ -291,27 +332,7 @@ Method (NPON, 0, Serialized)
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}
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Else
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{
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SRCC (SRCCLK_ENABLE)
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PGON ()
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\_SB.PCI0.PEG0.LD23 ()
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/* Wait for dGPU to reappear on the bus */
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Local0 = 50
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While (NVID != PCI_VID_NVIDIA)
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{
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Stall (100)
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Local0--
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If (Local0 == 0)
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{
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Break
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}
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}
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/* Restore the PEG LTR enable bit */
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LREN = SLTR
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/* Clear recoverable errors detected bit */
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CEDR = 1
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GCOO ()
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}
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}
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@ -330,11 +351,7 @@ Method (NPOF, 0, Serialized)
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}
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Else
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{
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/* Save the PEG port's LTR setting */
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SLTR = LREN
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\_SB.PCI0.PEG0.DL23 ()
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PGOF ()
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SRCC (SRCCLK_DISABLE)
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GCOI ()
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}
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}
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@ -380,7 +397,7 @@ Method (_PS3, 0, NotSerialized)
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/* Poweroff or deferred GC6 entry */
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NPOF ()
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/* Because _PS3 ran _OFF, _PS0 must run _ON */
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/* Because _PS3 ran NPOF, _PS0 must run NPON */
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OPS0 = OPTIMUS_CONTROL_RUN_PS0
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/* OPCS is one-shot, so reset it */
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