soc/intel/{skl,kbl}: ensure C1E is disabled after S3 resume

C1E is disabled by the kernel driver intel_idle at boot.  This does not
address the S3 resume case, so we lose state and C1E is enabled after S3
resume.

Disable C1E for SKL and KBL.  This gives a coherent state before
and after S3 resume.

TEST='iotools rdmsr cpu 0x1fc'. Returns the same value after boot and S3
resume with bit [1] set to zero (0x20005d).

Change-Id: I1343f343bfac9b787f13c15b812c0a201dcccb38
Signed-off-by: Cole Nelson <colex.nelson@intel.com>
Reviewed-on: https://review.coreboot.org/27125
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Cole Nelson 2018-06-15 15:51:54 -07:00 committed by Patrick Georgi
parent 4cdd2f8ce1
commit 63b6fea5c9
1 changed files with 1 additions and 1 deletions

View File

@ -310,9 +310,9 @@ static void configure_misc(void)
msr.hi = 0; msr.hi = 0;
wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
/* Enable PROCHOT */
msr = rdmsr(MSR_POWER_CTL); msr = rdmsr(MSR_POWER_CTL);
msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/ msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/
msr.lo &= ~POWER_CTL_C1E_MASK; /* Disable C1E */
msr.lo |= (1 << 23); /* Lock it */ msr.lo |= (1 << 23); /* Lock it */
wrmsr(MSR_POWER_CTL, msr); wrmsr(MSR_POWER_CTL, msr);
} }