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nb/intel/sandybridge: Improve cbmem_top_chipset calculation 

Lock bit in TSEGMB register wasn't accounted for in `cbmem_top_chipset`.
Align down TSEG base to 1 MiB granularity to avoid surprises.

Change-Id: I74882db99502ae77c94d43d850533a4f76da2773
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons 2020-10-01 20:23:18 +02:00
parent e31506cd51
commit 63c0dc9dba
1 changed files with 10 additions and 12 deletions
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22
src/northbridge/intel/sandybridge/memmap.c
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@ -13,20 +13,10 @@
#include <stddef.h>
#include <stdint.h>
static uintptr_t smm_region_start(void)
{
/* Base of TSEG is top of usable DRAM */
return pci_read_config32(HOST_BRIDGE, TSEGMB);
}
void *cbmem_top_chipset(void)
{
return (void *)smm_region_start();
}
static uintptr_t northbridge_get_tseg_base(void)
{
return ALIGN_DOWN(smm_region_start(), 1 * MiB);
/* TSEG has 1 MiB granularity, and bit 0 is a lock */
return ALIGN_DOWN(pci_read_config32(HOST_BRIDGE, TSEGMB), 1 * MiB);
}
static size_t northbridge_get_tseg_size(void)
@ -34,6 +24,14 @@ static size_t northbridge_get_tseg_size(void)
return CONFIG_SMM_TSEG_SIZE;
}
void *cbmem_top_chipset(void)
{
/* If DPR is disabled, base of TSEG is top of usable DRAM */
uintptr_t top_of_ram = northbridge_get_tseg_base();
return (void *)top_of_ram;
}
void smm_region(uintptr_t *start, size_t *size)
{
*start = northbridge_get_tseg_base();