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mb/google/sarien: Fix SSD power leakage in S5 

Turn off SSD power in S5.

BUG=b:133389422
TEST=measure H13 is low in S5

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I40b5381cac33b0eac962a7730ee5c57e60e6d375
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Eric Lai 2019-05-23 15:31:40 +08:00 committed by Duncan Laurie
parent 9e5b06297d
commit 63cba976b1
2 changed files with 16 additions and 0 deletions
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8
src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl
View File

@ -15,6 +15,8 @@
#define CAM_EN GPP_B11 /* Active low */
#define TS_PD GPP_E7
#define SSD_EN GPP_H13
#define SSD_RST GPP_H12
/* Method called from LPIT prior to enter s0ix state */
Method (MS0X, 1)
@ -35,6 +37,12 @@ Method (MPTS, 1)
/* Clear touch screen pd pin to avoid leakage */
\_SB.PCI0.CTXS (TS_PD)
/* Clear SSD EN adn RST pin to avoid leakage */
If (Arg0 == 5) {
\_SB.PCI0.CTXS (SSD_EN)
\_SB.PCI0.CTXS (SSD_RST)
}
}
/* Method called from _WAK prior to wakeup */

8
src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl
View File

@ -15,6 +15,8 @@
#define CAM_EN GPP_B11 /* Active low */
#define TS_PD GPP_E7
#define SSD_EN GPP_H13
#define SSD_RST GPP_H12
/* Method called from LPIT prior to enter s0ix state */
Method (MS0X, 1)
@ -35,6 +37,12 @@ Method (MPTS, 1)
/* Clear touch screen pd pin to avoid leakage */
\_SB.PCI0.CTXS (TS_PD)
/* Clear SSD EN adn RST pin to avoid leakage */
If (Arg0 == 5) {
\_SB.PCI0.CTXS (SSD_EN)
\_SB.PCI0.CTXS (SSD_RST)
}
}
/* Method called from _WAK prior to wakeup */