mb/google/sarien: Fix SSD power leakage in S5
Turn off SSD power in S5. BUG=b:133389422 TEST=measure H13 is low in S5 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I40b5381cac33b0eac962a7730ee5c57e60e6d375 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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@ -15,6 +15,8 @@
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#define CAM_EN GPP_B11 /* Active low */
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#define CAM_EN GPP_B11 /* Active low */
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#define TS_PD GPP_E7
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#define TS_PD GPP_E7
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#define SSD_EN GPP_H13
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#define SSD_RST GPP_H12
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/* Method called from LPIT prior to enter s0ix state */
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/* Method called from LPIT prior to enter s0ix state */
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Method (MS0X, 1)
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Method (MS0X, 1)
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@ -35,6 +37,12 @@ Method (MPTS, 1)
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/* Clear touch screen pd pin to avoid leakage */
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/* Clear touch screen pd pin to avoid leakage */
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\_SB.PCI0.CTXS (TS_PD)
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\_SB.PCI0.CTXS (TS_PD)
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/* Clear SSD EN adn RST pin to avoid leakage */
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If (Arg0 == 5) {
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\_SB.PCI0.CTXS (SSD_EN)
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\_SB.PCI0.CTXS (SSD_RST)
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}
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}
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}
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/* Method called from _WAK prior to wakeup */
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/* Method called from _WAK prior to wakeup */
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@ -15,6 +15,8 @@
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#define CAM_EN GPP_B11 /* Active low */
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#define CAM_EN GPP_B11 /* Active low */
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#define TS_PD GPP_E7
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#define TS_PD GPP_E7
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#define SSD_EN GPP_H13
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#define SSD_RST GPP_H12
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/* Method called from LPIT prior to enter s0ix state */
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/* Method called from LPIT prior to enter s0ix state */
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Method (MS0X, 1)
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Method (MS0X, 1)
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@ -35,6 +37,12 @@ Method (MPTS, 1)
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/* Clear touch screen pd pin to avoid leakage */
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/* Clear touch screen pd pin to avoid leakage */
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\_SB.PCI0.CTXS (TS_PD)
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\_SB.PCI0.CTXS (TS_PD)
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/* Clear SSD EN adn RST pin to avoid leakage */
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If (Arg0 == 5) {
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\_SB.PCI0.CTXS (SSD_EN)
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\_SB.PCI0.CTXS (SSD_RST)
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}
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}
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}
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/* Method called from _WAK prior to wakeup */
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/* Method called from _WAK prior to wakeup */
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