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soc/intel/tigerlake: Add CmdMirror option in chip.h 

Provide CmdMirror option in chip.h so that it can control CmdMirror FSP
UPD via dev tree.

BUG=b:156435028
BRANCH=none
TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Idae9fa439f077f8f3fb16fe74c2f263c008cd5f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42276
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
David Wu 2020-06-11 14:46:24 +08:00 committed by Patrick Georgi
parent feecdc2c0b
commit 63ce260a3e
2 changed files with 6 additions and 0 deletions
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3
src/soc/intel/tigerlake/chip.h
View File

@ -115,6 +115,9 @@ struct soc_intel_tigerlake_config {
/* Rank Margin Tool. 1:Enable, 0:Disable */
uint8_t RMT;
/* Command Pins Mirrored */
uint32_t CmdMirror;
/* USB related */
struct usb2_port_config usb2_ports[16];
struct usb3_port_config usb3_ports[10];

3
src/soc/intel/tigerlake/romstage/fsp_params.c
View File

@ -196,6 +196,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
/* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */
m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
/* Command Pins Mirrored */
m_cfg->CmdMirror[0] = config->CmdMirror;
}
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)