[REMOVAL] iwill/dk8s2
As announced in http://permalink.gmane.org/gmane.linux.bios/81918 I am removing all boards older than 10 years from the tree. Change-Id: I4a942150590fb69ff97279ff2b48b3be83abafa4 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12372 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Stefan Reinauer
parent
029f3550ef
commit
63d5088bb6
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@ -1,52 +0,0 @@
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if BOARD_IWILL_DK8S2
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select CPU_AMD_SOCKET_940
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select NORTHBRIDGE_AMD_AMDK8
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select SOUTHBRIDGE_AMD_AMD8111
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select SOUTHBRIDGE_AMD_AMD8131
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select SUPERIO_WINBOND_W83627HF
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select PARALLEL_CPU_INIT
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select HAVE_PIRQ_TABLE
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select HAVE_OPTION_TABLE
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select HAVE_MP_TABLE
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select SB_HT_CHAIN_UNITID_OFFSET_ONLY
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select DRIVERS_ATI_RAGEXL
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select BOARD_ROMSIZE_KB_512
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select RAMINIT_SYSINFO
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select QRANK_DIMM_SUPPORT
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config MAINBOARD_DIR
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string
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default iwill/dk8s2
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config APIC_ID_OFFSET
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hex
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default 0x0
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config MAINBOARD_PART_NUMBER
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string
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default "DK8S2"
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config MAX_CPUS
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int
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default 2
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config MAX_PHYSICAL_CPUS
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int
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default 2
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x20
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config HT_CHAIN_UNITID_BASE
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hex
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default 0x1
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config IRQ_SLOT_COUNT
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int
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default 12
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endif # BOARD_IWILL_DK8S2
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config BOARD_IWILL_DK8S2
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bool "DK8S2"
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@ -1,2 +0,0 @@
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Category: server
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Board URL: http://web.archive.org/web/20060509143427/http://www.iwill.net/product_2.asp?p_id=42&sp=Y
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@ -1,60 +0,0 @@
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entries
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0 384 r 0 reserved_memory
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384 1 e 4 boot_option
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388 4 r 0 reboot_bits
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392 3 e 5 baud_rate
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395 1 e 1 hw_scrubber
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396 1 e 1 interleave_chip_selects
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397 2 e 8 max_mem_clock
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399 1 e 2 multi_core
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400 1 e 1 power_on_after_fail
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412 4 e 6 debug_level
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440 4 e 9 slow_cpu
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444 1 e 1 nmi
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445 1 e 1 iommu
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456 1 e 1 ECC_memory
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728 256 h 0 user_data
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984 16 h 0 check_sum
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# Reserve the extended AMD configuration registers
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1000 24 r 0 amd_reserved
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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5 0 115200
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5 1 57600
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5 2 38400
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5 3 19200
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5 4 9600
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5 5 4800
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5 6 2400
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5 7 1200
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6 6 Notice
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6 7 Info
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6 8 Debug
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6 9 Spew
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8 0 DDR400
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8 1 DDR333
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8 2 DDR266
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8 3 DDR200
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9 0 off
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9 1 87.5%
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9 2 75.0%
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9 3 62.5%
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9 4 50.0%
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9 5 37.5%
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9 6 25.0%
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9 7 12.5%
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checksums
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checksum 392 983 984
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@ -1,75 +0,0 @@
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chip northbridge/amd/amdk8/root_complex
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device cpu_cluster 0 on
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chip cpu/amd/socket_940
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device lapic 0 on end
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end
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end
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device domain 0 on
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subsystemid 0x161f 0x3016 inherit
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chip northbridge/amd/amdk8
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device pci 18.0 on # LDT 0
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chip southbridge/amd/amd8131
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device pci 0.0 on end
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device pci 0.1 on end
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device pci 1.0 on end
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device pci 1.1 on end
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end
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chip southbridge/amd/amd8111
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# this "device pci 0.0" is the parent the next one
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# PCI bridge
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device pci 0.0 on
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device pci 0.0 on end
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device pci 0.1 on end
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device pci 0.2 on end
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device pci 1.0 off end
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end
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device pci 1.0 on
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chip superio/winbond/w83627hf
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device pnp 2e.0 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 off # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.2 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 off # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x72 = 12
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end
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device pnp 2e.6 off end # CIR
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device pnp 2e.7 off end # GAME_MIDI_GIPO1
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device pnp 2e.8 off end # GPIO2
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device pnp 2e.9 off end # GPIO3
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device pnp 2e.a off end # ACPI
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device pnp 2e.b on # HW Monitor
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io 0x60 = 0x290
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end
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end
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end
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device pci 1.1 on end
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device pci 1.2 on end
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device pci 1.3 on end
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device pci 1.5 off end
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device pci 1.6 off end
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end
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end # LDT0
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device pci 18.0 on end # LDT1
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device pci 18.0 on end # LDT2
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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end
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end
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end
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#include <arch/pirq_routing.h>
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static const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
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0x00, /* Where the interrupt router lies (bus) */
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(0x07<<3)|0x3, /* Where the interrupt router lies (dev) */
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0, /* IRQs devoted exclusively to PCI usage */
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0x1022, /* Vendor */
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0x746b, /* Device */
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0, /* Miniport data */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0x6d, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
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{
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/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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{0x00,(0x07<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0x0def8}}, 0x0, 0x0},
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{0x03,(0x00<<3)|0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x04, 0x0def8}}, 0x0, 0x0},
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{0x02,(0x01<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0x0def8}}, 0x1, 0x0},
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{0x02,(0x02<<3)|0x0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x2, 0x0},
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{0x01,(0x01<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0x0def8}}, 0x3, 0x0},
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{0x01,(0x02<<3)|0x0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x4, 0x0},
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{0x03,(0x04<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0x0def8}}, 0x5, 0x0},
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{0x03,(0x05<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0x0def8}}, 0x6, 0x0},
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{0x03,(0x06<<3)|0x0, {{0x03, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
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{0x02,(0x03<<3)|0x0, {{0x04, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
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{0x02,(0x04<<3)|0x0, {{0x01, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
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{0x02,(0x05<<3)|0x0, {{0x02, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
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}
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr, &intel_irq_routing_table);
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}
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@ -1,166 +0,0 @@
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#include <console/console.h>
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#include <arch/smp/mpspec.h>
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#include <arch/ioapic.h>
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#include <device/pci.h>
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#include <string.h>
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#include <stdint.h>
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static void *smp_write_config_table(void *v)
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{
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struct mp_config_table *mc;
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int bus_isa;
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unsigned char bus_8131_1;
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unsigned char bus_8131_2;
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unsigned char bus_8111_1;
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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mptable_init(mc, LOCAL_APIC_ADDR);
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smp_write_processors(mc);
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{
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device_t dev;
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/* 8111 */
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dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
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if (dev) {
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bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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}
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else {
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printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
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bus_8111_1 = 4;
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}
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/* 8131-1 */
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dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
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if (dev) {
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bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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}
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else {
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printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
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bus_8131_1 = 2;
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}
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/* 8131-2 */
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dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
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if (dev) {
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bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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}
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else {
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printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
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bus_8131_2 = 3;
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}
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}
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mptable_write_buses(mc, NULL, &bus_isa);
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/* IOAPIC handling */
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smp_write_ioapic(mc, 2, 0x11, VIO_APIC_VADDR);
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{
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device_t dev;
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struct resource *res;
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/* 8131 apic 3 */
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dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res) {
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smp_write_ioapic(mc, 0x03, 0x11,
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res2mmio(res, 0, 0));
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}
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}
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/* 8131 apic 4 */
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dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res) {
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smp_write_ioapic(mc, 0x04, 0x11,
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res2mmio(res, 0, 0));
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}
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}
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}
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mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
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/* Standard local interrupt assignments */
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mptable_lintsrc(mc, bus_isa);
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/* PCI Slot 1 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_2, (1<<2)|0, 0x02, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_2, (1<<2)|1, 0x02, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_2, (1<<2)|2, 0x02, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_2, (1<<2)|3, 0x02, 0x10);
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/* PCI Slot 2 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_2, (2<<2)|0, 0x02, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_2, (2<<2)|1, 0x02, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_2, (2<<2)|2, 0x02, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_2, (2<<2)|3, 0x02, 0x11);
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/* PCI Slot 3 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_1, (1<<2)|0, 0x02, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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|
||||||
bus_8131_1, (1<<2)|1, 0x02, 0x12);
|
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
|
||||||
bus_8131_1, (1<<2)|2, 0x02, 0x13);
|
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
|
||||||
bus_8131_1, (1<<2)|3, 0x02, 0x10);
|
|
||||||
|
|
||||||
/* PCI Slot 4 */
|
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
|
||||||
bus_8131_1, (2<<2)|0, 0x02, 0x12);
|
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
|
||||||
bus_8131_1, (2<<2)|1, 0x02, 0x13);
|
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
|
||||||
bus_8131_1, (2<<2)|2, 0x02, 0x10);
|
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
|
||||||
bus_8131_1, (2<<2)|3, 0x02, 0x11);
|
|
||||||
|
|
||||||
/* PCI Slot 5 */
|
|
||||||
// FIXME get the irqs right, it's just hacked to work for now
|
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
|
||||||
bus_8111_1, (5<<2)|0, 0x02, 0x11);
|
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
|
||||||
bus_8111_1, (5<<2)|1, 0x02, 0x12);
|
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
|
||||||
bus_8111_1, (5<<2)|2, 0x02, 0x13);
|
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
|
||||||
bus_8111_1, (5<<2)|3, 0x02, 0x10);
|
|
||||||
|
|
||||||
/* PCI Slot 6 */
|
|
||||||
// FIXME get the irqs right, it's just hacked to work for now
|
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
|
||||||
bus_8111_1, (4<<2)|0, 0x02, 0x10);
|
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
|
||||||
bus_8111_1, (4<<2)|1, 0x02, 0x11);
|
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
|
||||||
bus_8111_1, (4<<2)|2, 0x02, 0x12);
|
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
|
||||||
bus_8111_1, (4<<2)|3, 0x02, 0x13);
|
|
||||||
|
|
||||||
/* On board nics */
|
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
|
||||||
bus_8131_1, (3<<2)|0, 0x02, 0x13);
|
|
||||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
|
||||||
bus_8131_1, (4<<2)|0, 0x02, 0x13);
|
|
||||||
|
|
||||||
/* There is no extension information... */
|
|
||||||
|
|
||||||
/* Compute the checksums */
|
|
||||||
return mptable_finalize(mc);
|
|
||||||
}
|
|
||||||
|
|
||||||
unsigned long write_smp_table(unsigned long addr)
|
|
||||||
{
|
|
||||||
void *v;
|
|
||||||
v = smp_write_floating_table(addr, 0);
|
|
||||||
return (unsigned long)smp_write_config_table(v);
|
|
||||||
}
|
|
||||||
|
|
@ -1,164 +0,0 @@
|
||||||
#include <stdint.h>
|
|
||||||
#include <string.h>
|
|
||||||
#include <device/pci_def.h>
|
|
||||||
#include <device/pci_ids.h>
|
|
||||||
#include <arch/io.h>
|
|
||||||
#include <device/pnp_def.h>
|
|
||||||
#include <pc80/mc146818rtc.h>
|
|
||||||
#include <console/console.h>
|
|
||||||
#include <cpu/amd/model_fxx_rev.h>
|
|
||||||
#include "southbridge/amd/amd8111/early_smbus.c"
|
|
||||||
#include <northbridge/amd/amdk8/raminit.h>
|
|
||||||
#include "northbridge/amd/amdk8/reset_test.c"
|
|
||||||
#include <cpu/x86/bist.h>
|
|
||||||
#include <delay.h>
|
|
||||||
#include "northbridge/amd/amdk8/debug.c"
|
|
||||||
#include <superio/winbond/common/winbond.h>
|
|
||||||
#include <superio/winbond/w83627hf/w83627hf.h>
|
|
||||||
#include "northbridge/amd/amdk8/setup_resource_map.c"
|
|
||||||
#include "southbridge/amd/amd8111/early_ctrl.c"
|
|
||||||
|
|
||||||
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* GPIO28 of 8111 will control H0_MEMRESET_L
|
|
||||||
* GPIO29 of 8111 will control H1_MEMRESET_L
|
|
||||||
*/
|
|
||||||
static void memreset_setup(void)
|
|
||||||
{
|
|
||||||
if (is_cpu_pre_c0()) {
|
|
||||||
/* Set the memreset low. */
|
|
||||||
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
|
|
||||||
/* Ensure the BIOS has control of the memory lines. */
|
|
||||||
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
|
|
||||||
} else {
|
|
||||||
/* Ensure the CPU has control of the memory lines. */
|
|
||||||
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static void memreset(int controllers, const struct mem_controller *ctrl)
|
|
||||||
{
|
|
||||||
if (is_cpu_pre_c0()) {
|
|
||||||
udelay(800);
|
|
||||||
/* Set memreset high. */
|
|
||||||
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
|
|
||||||
udelay(90);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static void activate_spd_rom(const struct mem_controller *ctrl) { }
|
|
||||||
|
|
||||||
static inline int spd_read_byte(unsigned device, unsigned address)
|
|
||||||
{
|
|
||||||
return smbus_read_byte(device, address);
|
|
||||||
}
|
|
||||||
|
|
||||||
#include <northbridge/amd/amdk8/amdk8.h>
|
|
||||||
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
|
||||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
|
||||||
#include "northbridge/amd/amdk8/raminit.c"
|
|
||||||
#include "lib/generic_sdram.c"
|
|
||||||
#include "northbridge/amd/amdk8/resourcemap.c"
|
|
||||||
#include "cpu/amd/dualcore/dualcore.c"
|
|
||||||
#include <spd.h>
|
|
||||||
#include "cpu/amd/model_fxx/init_cpus.c"
|
|
||||||
#include "cpu/amd/model_fxx/fidvid.c"
|
|
||||||
|
|
||||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
|
||||||
{
|
|
||||||
static const uint16_t spd_addr[] = {
|
|
||||||
// first node
|
|
||||||
DIMM0, DIMM2, 0, 0,
|
|
||||||
DIMM1, DIMM3, 0, 0,
|
|
||||||
|
|
||||||
// second node
|
|
||||||
DIMM4, DIMM6, 0, 0,
|
|
||||||
DIMM5, DIMM7, 0, 0,
|
|
||||||
};
|
|
||||||
|
|
||||||
struct sys_info *sysinfo = &sysinfo_car;
|
|
||||||
int needs_reset;
|
|
||||||
unsigned bsp_apicid = 0;
|
|
||||||
|
|
||||||
if (bist == 0)
|
|
||||||
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
|
|
||||||
|
|
||||||
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
|
||||||
console_init();
|
|
||||||
|
|
||||||
/* Halt if there was a built in self test failure */
|
|
||||||
report_bist_failure(bist);
|
|
||||||
|
|
||||||
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
|
|
||||||
|
|
||||||
setup_default_resource_map();
|
|
||||||
|
|
||||||
printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
|
|
||||||
|
|
||||||
setup_coherent_ht_domain(); // routing table and start other core0
|
|
||||||
|
|
||||||
wait_all_core0_started();
|
|
||||||
#if CONFIG_LOGICAL_CPUS
|
|
||||||
// It is said that we should start core1 after all core0 launched
|
|
||||||
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
|
|
||||||
* So here need to make sure last core0 is started, esp for two way system,
|
|
||||||
* (there may be apic id conflicts in that case)
|
|
||||||
*/
|
|
||||||
start_other_cores();
|
|
||||||
wait_all_other_cores_started(bsp_apicid);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* it will set up chains and store link pair for optimization later */
|
|
||||||
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
|
|
||||||
|
|
||||||
#if CONFIG_SET_FIDVID
|
|
||||||
{
|
|
||||||
msr_t msr;
|
|
||||||
msr=rdmsr(0xc0010042);
|
|
||||||
printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
|
|
||||||
}
|
|
||||||
enable_fid_change();
|
|
||||||
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
|
|
||||||
init_fidvid_bsp(bsp_apicid);
|
|
||||||
// show final fid and vid
|
|
||||||
{
|
|
||||||
msr_t msr;
|
|
||||||
msr=rdmsr(0xc0010042);
|
|
||||||
printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
needs_reset = optimize_link_coherent_ht();
|
|
||||||
needs_reset |= optimize_link_incoherent_ht(sysinfo);
|
|
||||||
|
|
||||||
// fidvid change will issue one LDTSTOP and the HT change will be effective too
|
|
||||||
if (needs_reset) {
|
|
||||||
printk(BIOS_INFO, "ht reset -\n");
|
|
||||||
soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
|
|
||||||
}
|
|
||||||
|
|
||||||
allow_all_aps_stop(bsp_apicid);
|
|
||||||
|
|
||||||
//It's the time to set ctrl in sysinfo now;
|
|
||||||
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
|
|
||||||
|
|
||||||
enable_smbus();
|
|
||||||
|
|
||||||
#if 0
|
|
||||||
dump_smbus_registers();
|
|
||||||
#endif
|
|
||||||
|
|
||||||
memreset_setup();
|
|
||||||
|
|
||||||
//do we need apci timer, tsc...., only debug need it for better output
|
|
||||||
/* all ap stopped? */
|
|
||||||
init_timer(); // Need to use TMICT to synchronize FID/VID
|
|
||||||
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
|
|
||||||
|
|
||||||
#if 0
|
|
||||||
dump_pci_devices();
|
|
||||||
#endif
|
|
||||||
|
|
||||||
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
|
|
||||||
}
|
|
||||||
Loading…
Reference in New Issue