northbridge/intel/i82830: Unify UDELAY selection
Instead of manually including udelay_io.c in each romstage, select UDELAY_IO for all i830 boards in the chipset. Change-Id: I0a63ddd3c5e43ea65f776385f54eceb6569751ac Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13783 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select SOUTHBRIDGE_INTEL_I82801DX
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select SUPERIO_SMSC_SMSCSUPERIO
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select HAVE_PIRQ_TABLE
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select UDELAY_TSC
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select BOARD_ROMSIZE_KB_1024
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config MAINBOARD_DIR
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@ -14,6 +14,8 @@
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* GNU General Public License for more details.
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*/
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#include <delay.h>
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#define PME_DEV PNP_DEV(0x2e, 0x0a)
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#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */
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#define ICH_IO_BASE_ADDR 0x00000500 /* GPIO base address register */
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@ -19,7 +19,6 @@
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#include <device/pci_def.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include "drivers/pc80/udelay_io.c"
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#include <console/console.h>
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#include <lib.h>
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#include <superio/smsc/smscsuperio/smscsuperio.h>
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@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select SOUTHBRIDGE_INTEL_I82801DX
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select SUPERIO_SMSC_SMSCSUPERIO
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select HAVE_PIRQ_TABLE
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select UDELAY_TSC
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select BOARD_ROMSIZE_KB_512
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select INTEL_INT15
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@ -14,6 +14,8 @@
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* GNU General Public License for more details.
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*/
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#include <delay.h>
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#define PME_DEV PNP_DEV(0x2e, 0x0a)
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#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */
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#define ICH_IO_BASE_ADDR 0x00000500 /* GPIO base address register */
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@ -19,7 +19,6 @@
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#include <device/pci_def.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include "drivers/pc80/udelay_io.c"
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#include <console/console.h>
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#include <lib.h>
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#include <superio/smsc/smscsuperio/smscsuperio.h>
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@ -2,6 +2,7 @@ config NORTHBRIDGE_INTEL_I82830
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bool
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select HAVE_DEBUG_RAM_SETUP
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select LATE_CBMEM_INIT
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select UDELAY_IO
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choice
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prompt "Onboard graphics"
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