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soc/amd/*/cpu: factor out common noncar mp_init_cpus 

Since all non-CAR AMD SoCs have the same mp_init_cpus implementation,
factor it out and move it to a common location.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibf4fa667106769989c916d941addb1cba38b7f13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
This commit is contained in:
Felix Held 2023-09-20 18:51:27 +02:00
parent 05a3c1de38
commit 63e77b0252
7 changed files with 27 additions and 124 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
src/soc/amd/cezanne/cpu.c
View File

@ -1,39 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
#include <amdblocks/cpu.h>
#include <amdblocks/iomap.h>
#include <amdblocks/mca.h>
#include <console/console.h>
#include <cpu/amd/microcode.h>
#include <cpu/cpu.h>
#include <cpu/x86/mp.h>
#include <cpu/x86/mtrr.h>
#include <device/device.h>
#include <soc/cpu.h>
#include <soc/iomap.h>
_Static_assert(CONFIG_MAX_CPUS == 16, "Do not override MAX_CPUS. To reduce the number of "
"available cores, use the downcore_mode and disable_smt devicetree settings instead.");
/* MP and SMM loading initialization */
void mp_init_cpus(struct bus *cpu_bus)
{
extern const struct mp_ops amd_mp_ops_with_smm;
if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS)
die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"mp_init_with_smm failed. Halting.\n");
/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
mtrr_use_temp_range(FLASH_BELOW_4GB_MAPPING_REGION_BASE,
FLASH_BELOW_4GB_MAPPING_REGION_SIZE, MTRR_TYPE_WRPROT);
/* SMMINFO only needs to be set up when booting from S5 */
if (!acpi_is_wakeup_s3())
apm_control(APM_CNT_SMMINFO);
}
static void zen_2_3_init(struct device *dev)
{
check_mca();

1
src/soc/amd/common/block/cpu/noncar/Makefile.inc
View File

@ -10,5 +10,6 @@ romstage-y += memmap.c
ramstage-y += cpu.c
romstage-y += cpu.c
ramstage-y += memmap.c
ramstage-y += mpinit.c
endif # CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR

26
src/soc/amd/common/block/cpu/noncar/mpinit.c Normal file
View File

@ -0,0 +1,26 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
#include <amdblocks/iomap.h>
#include <console/console.h>
#include <cpu/x86/mp.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <device/device.h>
#include <types.h>
void mp_init_cpus(struct bus *cpu_bus)
{
extern const struct mp_ops amd_mp_ops_with_smm;
if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS)
die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"mp_init_with_smm failed. Halting.\n");
/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
mtrr_use_temp_range(FLASH_BELOW_4GB_MAPPING_REGION_BASE,
FLASH_BELOW_4GB_MAPPING_REGION_SIZE, MTRR_TYPE_WRPROT);
/* SMMINFO only needs to be set up when booting from S5 */
if (!acpi_is_wakeup_s3())
apm_control(APM_CNT_SMMINFO);
}

25
src/soc/amd/glinda/cpu.c
View File

@ -2,41 +2,16 @@
/* TODO: Update for Glinda */
#include <acpi/acpi.h>
#include <amdblocks/cpu.h>
#include <amdblocks/iomap.h>
#include <amdblocks/mca.h>
#include <console/console.h>
#include <cpu/amd/microcode.h>
#include <cpu/cpu.h>
#include <cpu/x86/mp.h>
#include <cpu/x86/mtrr.h>
#include <acpi/acpi.h>
#include <device/device.h>
#include <soc/cpu.h>
#include <soc/iomap.h>
_Static_assert(CONFIG_MAX_CPUS == 8, "Do not override MAX_CPUS. To reduce the number of "
"available cores, use the downcore_mode and disable_smt devicetree settings instead.");
/* MP and SMM loading initialization */
void mp_init_cpus(struct bus *cpu_bus)
{
extern const struct mp_ops amd_mp_ops_with_smm;
if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS)
die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"mp_init_with_smm failed. Halting.\n");
/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
mtrr_use_temp_range(FLASH_BELOW_4GB_MAPPING_REGION_BASE,
FLASH_BELOW_4GB_MAPPING_REGION_SIZE, MTRR_TYPE_WRPROT);
/* SMMINFO only needs to be set up when booting from S5 */
if (!acpi_is_wakeup_s3())
apm_control(APM_CNT_SMMINFO);
}
static void zen_2_3_init(struct device *dev)
{
check_mca();

25
src/soc/amd/mendocino/cpu.c
View File

@ -1,40 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
#include <amdblocks/cpu.h>
#include <amdblocks/iomap.h>
#include <amdblocks/mca.h>
#include <console/console.h>
#include <cpu/amd/microcode.h>
#include <cpu/cpu.h>
#include <cpu/x86/mp.h>
#include <cpu/x86/mtrr.h>
#include <acpi/acpi.h>
#include <device/device.h>
#include <soc/cpu.h>
#include <soc/iomap.h>
_Static_assert(CONFIG_MAX_CPUS == 8, "Do not override MAX_CPUS. To reduce the number of "
"available cores, use the downcore_mode and disable_smt devicetree settings instead.");
/* MP and SMM loading initialization */
void mp_init_cpus(struct bus *cpu_bus)
{
extern const struct mp_ops amd_mp_ops_with_smm;
if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS)
die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"mp_init_with_smm failed. Halting.\n");
/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
mtrr_use_temp_range(FLASH_BELOW_4GB_MAPPING_REGION_BASE,
FLASH_BELOW_4GB_MAPPING_REGION_SIZE, MTRR_TYPE_WRPROT);
/* SMMINFO only needs to be set up when booting from S5 */
if (!acpi_is_wakeup_s3())
apm_control(APM_CNT_SMMINFO);
}
static void zen_2_3_init(struct device *dev)
{
check_mca();

25
src/soc/amd/phoenix/cpu.c
View File

@ -2,41 +2,16 @@
/* TODO: Update for Phoenix */
#include <acpi/acpi.h>
#include <amdblocks/cpu.h>
#include <amdblocks/iomap.h>
#include <amdblocks/mca.h>
#include <console/console.h>
#include <cpu/amd/microcode.h>
#include <cpu/cpu.h>
#include <cpu/x86/mp.h>
#include <cpu/x86/mtrr.h>
#include <acpi/acpi.h>
#include <device/device.h>
#include <soc/cpu.h>
#include <soc/iomap.h>
_Static_assert(CONFIG_MAX_CPUS == 16, "Do not override MAX_CPUS. To reduce the number of "
"available cores, use the downcore_mode and disable_smt devicetree settings instead.");
/* MP and SMM loading initialization */
void mp_init_cpus(struct bus *cpu_bus)
{
extern const struct mp_ops amd_mp_ops_with_smm;
if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS)
die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"mp_init_with_smm failed. Halting.\n");
/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
mtrr_use_temp_range(FLASH_BELOW_4GB_MAPPING_REGION_BASE,
FLASH_BELOW_4GB_MAPPING_REGION_SIZE, MTRR_TYPE_WRPROT);
/* SMMINFO only needs to be set up when booting from S5 */
if (!acpi_is_wakeup_s3())
apm_control(APM_CNT_SMMINFO);
}
static void zen_2_3_init(struct device *dev)
{
check_mca();

25
src/soc/amd/picasso/cpu.c
View File

@ -1,40 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
#include <amdblocks/cpu.h>
#include <amdblocks/iomap.h>
#include <amdblocks/mca.h>
#include <console/console.h>
#include <cpu/amd/microcode.h>
#include <cpu/cpu.h>
#include <cpu/x86/mp.h>
#include <cpu/x86/mtrr.h>
#include <device/device.h>
#include <soc/cpu.h>
#include <soc/iomap.h>
_Static_assert(CONFIG_MAX_CPUS == 8, "Do not override MAX_CPUS. To reduce the number of "
"available cores, use the downcore_mode and disable_smt devicetree settings instead.");
/* MP and SMM loading initialization. */
void mp_init_cpus(struct bus *cpu_bus)
{
extern const struct mp_ops amd_mp_ops_with_smm;
if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS)
die_with_post_code(POSTCODE_HW_INIT_FAILURE,
"mp_init_with_smm failed. Halting.\n");
/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
mtrr_use_temp_range(FLASH_BELOW_4GB_MAPPING_REGION_BASE,
FLASH_BELOW_4GB_MAPPING_REGION_SIZE, MTRR_TYPE_WRPROT);
/* SMMINFO only needs to be set up when booting from S5 */
if (!acpi_is_wakeup_s3())
apm_control(APM_CNT_SMMINFO);
}
static void model_17_init(struct device *dev)
{
check_mca();