superio/fintek/f71869ad: Make hwm devicetree configurable

Provision the configuration of the Fintek F71869AD Hardware Monitor's
configuration by way of devicetree.cb. Make use of this in the
jetway/nf81-t56n-lf board to properly control fan's.

Change-Id: Ic25b29d1b7a9145e0e209b490b25a2cbc46cb75c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5580
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

src/mainboard/jetway/nf81-t56n-lf/devicetree.cb

@@ -61,6 +61,18 @@ chip northbridge/amd/agesa/family14/root_complex
 								register "multi_function_register_3" = "0x24"
 								register "multi_function_register_4" = "0x00"
 								register "multi_function_register_5" = "0x60"
+# HWM configuration registers
+								register "hwm_smbus_address" = "0x98"
+								register "hwm_smbus_control_reg" = "0x02"
+								register "hwm_fan_type_sel_reg" = "0x00"
+								register "hwm_fan1_temp_adj_rate_reg" = "0x33"
+								register "hwm_fan_mode_sel_reg" = "0x07"
+								register "hwm_fan1_idx_rpm_mode" = "0x0e"
+								register "hwm_fan1_seg1_speed_count" = "0xff"
+								register "hwm_fan1_seg2_speed_count" = "0x0e"
+								register "hwm_fan1_seg3_speed_count" = "0x07"
+								register "hwm_fan1_temp_map_sel" = "0x8c"
+#
 # XXX: 4e is the default index port and .xy is the
 # LDN indexing the pnp_info array found in the superio.c
 # NB: Jetway board changes the default (0x4e) index port to (0x2e) by pin 124,

src/superio/fintek/f71869ad/Makefile.inc

@@ -19,4 +19,5 @@
 ##
 
 ramstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += f71869ad_multifunc.c
+ramstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += f71869ad_hwm.c
 ramstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += superio.c

src/superio/fintek/f71869ad/chip.h

@@ -33,6 +33,17 @@ struct superio_fintek_f71869ad_config {
 	uint8_t multi_function_register_3;
 	uint8_t multi_function_register_4;
 	uint8_t multi_function_register_5;
+	/* HWM configuration registers */
+	uint8_t hwm_smbus_address;
+	uint8_t hwm_smbus_control_reg;
+	uint8_t hwm_fan_type_sel_reg;
+	uint8_t hwm_fan1_temp_adj_rate_reg;
+	uint8_t hwm_fan_mode_sel_reg;
+	uint8_t hwm_fan1_idx_rpm_mode;
+	uint8_t hwm_fan1_seg1_speed_count;
+	uint8_t hwm_fan1_seg2_speed_count;
+	uint8_t hwm_fan1_seg3_speed_count;
+	uint8_t hwm_fan1_temp_map_sel;
 };
 
 #endif /* SUPERIO_FINTEK_F71869AD_CHIP_H */

src/superio/fintek/f71869ad/f71869ad_hwm.c

@@ -0,0 +1,112 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include "chip.h"
+#include "fintek_internal.h"
+
+/*
+ * The Fintek F71869AD Super I/O Hardware Monitor permits the configuration of
+ * three fans individually, where fan1 is typically taken as the CPU fan. Each
+ * fan is controlled by the relation:
+ *
+ * Tfan? = Tnow + (Ta - Tb)*Ct
+ *
+ * Parameters in this relation are specified in the devicetree.cb.
+ */
+
+/*
+ * Register CR01 ~ CR03 -> Configuration Registers
+ * Register CR0A ~ CR0F -> PECI/TSI Control Register
+ * Register CR10 ~ CR37 -> Voltage Setting Register
+ * Register CR40 ~ CR4E -> PECI 3.0 Command and Register
+ * Register CR60 ~ CR8E -> Temperature Setting Register
+ * Register CR90 ~ CRDF -> Fan Control Setting Register
+ */
+#define HWM_SMBUS_ADDR             0x08
+#define HWM_SMBUS_CONTROL_REG      0x0A
+#define HWM_FAN_TYPE_SEL_REG       0x94
+#define HWM_FAN1_TEMP_ADJ_RATE_REG 0x95
+#define HWM_FAN_MODE_SEL_REG       0x96
+#define HWM_FAN_FAULT_TIME_REG     0x9F /* bit7 FAN_PROG_SEL */
+#define HWM_FAN1_IDX_RPM_MODE      0xA3
+#define HWM_FAN1_SEG1_SPEED_COUNT  0xAA
+#define HWM_FAN1_SEG2_SPEED_COUNT  0xAB
+#define HWM_FAN1_SEG3_SPEED_COUNT  0xAC
+#define HWM_FAN1_TEMP_MAP_SEL      0xAF
+
+static void pnp_write_index(u16 port, u8 reg, u8 value)
+{
+	outb(reg, port);
+	outb(value, port + 1);
+}
+
+/* note: multifunc registers need to be tweaked before here */
+void f71869ad_hwm_init(device_t dev)
+{
+	struct superio_fintek_f71869ad_config *conf = dev->chip_info;
+	struct resource *res = find_resource(dev, PNP_IDX_IO0);
+
+	if (!res) {
+		printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n");
+		return;
+	}
+	u16 port = res->base; /* data-sheet default base = 0x229 */
+
+	printk(BIOS_INFO,
+		"Fintek F71869AD Super I/O HWM: Initializing Hardware Monitor..\n");
+	printk(BIOS_DEBUG,
+		"Fintek F71869AD Super I/O HWM: Base Address at 0x%x\n", port);
+
+	pnp_enter_conf_mode(dev);
+	pnp_set_logical_device(dev);
+
+	/* Fintek F71869AD HWM (ordered) programming sequence. */
+
+	/* SMBus Address p.53 */
+	pnp_write_index(port, HWM_SMBUS_ADDR, conf->hwm_smbus_address);
+	/* Configure pins 57/58 as PECI_REQ#/PECI (AMD_TSI) p.54 */
+	pnp_write_index(port, HWM_SMBUS_CONTROL_REG, conf->hwm_smbus_control_reg);
+	/* Tfan1 = Tnow + (Ta - Tb)*Ct where, */
+	/* FAN1_TEMP_SEL_DIG, FAN1_TEMP_SEL (Tnow) set to come from CR7Ah p.73 */
+	pnp_write_index(port, HWM_FAN1_TEMP_MAP_SEL, conf->hwm_fan1_temp_map_sel);
+	/* set FAN_PROG_SEL = 1 */
+	pnp_write_index(port, HWM_FAN_FAULT_TIME_REG, 0x8a);
+	/* FAN1_BASE_TEMP (Tb) set when FAN_PROG_SEL=1, p.64-65 */
+	pnp_write_index(port, HWM_FAN_TYPE_SEL_REG, conf->hwm_fan_type_sel_reg);
+	/* set TFAN1_ADJ_SEL (Ta) p.67 to use CR7Ah p.61 */
+	pnp_write_index(port, HWM_FAN_MODE_SEL_REG, conf->hwm_fan_mode_sel_reg);
+	/* TFAN1_ADJ_{UP,DOWN}_RATE (Ct=1/4 up & down) in 0x95 when FAN_PROG_SEL =
+		1, p.88 */
+	pnp_write_index(port, HWM_FAN1_TEMP_ADJ_RATE_REG, conf->hwm_fan1_temp_adj_rate_reg);
+	/* set FAN_PROG_SEL = 0 */
+	pnp_write_index(port, HWM_FAN_FAULT_TIME_REG, 0x0a);
+	/* FAN1 RPM mode p.70 */
+	pnp_write_index(port, HWM_FAN1_IDX_RPM_MODE, conf->hwm_fan1_idx_rpm_mode);
+	/* FAN1 Segment X Speed Count */
+	pnp_write_index(port, HWM_FAN1_SEG1_SPEED_COUNT, conf->hwm_fan1_seg1_speed_count);
+	pnp_write_index(port, HWM_FAN1_SEG2_SPEED_COUNT, conf->hwm_fan1_seg2_speed_count);
+	pnp_write_index(port, HWM_FAN1_SEG3_SPEED_COUNT, conf->hwm_fan1_seg3_speed_count);
+
+	pnp_exit_conf_mode(dev);
+}

src/superio/fintek/f71869ad/fintek_internal.h

@@ -25,5 +25,6 @@
 #include <device/pnp.h>
 
 void f71869ad_multifunc_init(device_t dev);
+void f71869ad_hwm_init(device_t dev);
 
 #endif /* SUPERIO_FINTEK_F71869AD_INTERNAL_H */

src/superio/fintek/f71869ad/superio.c

@@ -43,6 +43,7 @@ static void f71869ad_init(device_t dev)
 		break;
 	case F71869AD_HWM:
 		f71869ad_multifunc_init(dev);
+		f71869ad_hwm_init(dev);
 		break;
 	}
 }