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- kill the broken and duplicate 855pm directory. Hopefully I have kept 

the least broken one.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman 2004-10-27 01:58:26 +00:00
parent dfde9bb649
commit 63f2f721b4
8 changed files with 0 additions and 2412 deletions
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0
src/northbridge/intel/855pm/855pm.h
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4
src/northbridge/intel/855pm/Config.lb
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@ -1,4 +0,0 @@
config chip.h
object northbridge.o
#driver misc_control.o

5
src/northbridge/intel/855pm/chip.h
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struct northbridge_intel_855pm_config
{
};
extern struct chip_operations northbridge_intel_855pm_control;

164
src/northbridge/intel/855pm/debug.c
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@ -1,164 +0,0 @@
/*
* generic K8 debug code, used by mainboard specific auto.c
*
*/
#if 1
static void print_debug_pci_dev(unsigned dev)
{
print_debug("PCI: ");
print_debug_hex8((dev >> 16) & 0xff);
print_debug_char(':');
print_debug_hex8((dev >> 11) & 0x1f);
print_debug_char('.');
print_debug_hex8((dev >> 8) & 7);
}
static void print_pci_devices(void)
{
device_t dev;
for(dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
uint32_t id;
id = pci_read_config32(dev, PCI_VENDOR_ID);
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
(((id >> 16) & 0xffff) == 0xffff) ||
(((id >> 16) & 0xffff) == 0x0000)) {
continue;
}
print_debug_pci_dev(dev);
print_debug("\r\n");
}
}
static void dump_pci_device(unsigned dev)
{
int i;
print_debug_pci_dev(dev);
print_debug("\r\n");
for(i = 0; i <= 255; i++) {
unsigned char val;
if ((i & 0x0f) == 0) {
print_debug_hex8(i);
print_debug_char(':');
}
val = pci_read_config8(dev, i);
print_debug_char(' ');
print_debug_hex8(val);
if ((i & 0x0f) == 0x0f) {
print_debug("\r\n");
}
}
}
static void dump_pci_devices(void)
{
device_t dev;
for(dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
uint32_t id;
id = pci_read_config32(dev, PCI_VENDOR_ID);
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
(((id >> 16) & 0xffff) == 0xffff) ||
(((id >> 16) & 0xffff) == 0x0000)) {
continue;
}
dump_pci_device(dev);
}
}
static void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
print_debug("\r\n");
for(i = 0; i < 4; i++) {
unsigned device;
device = ctrl->channel0[i];
if (device) {
int j;
print_debug("dimm: ");
print_debug_hex8(i);
print_debug(".0: ");
print_debug_hex8(device);
for(j = 0; j < 256; j++) {
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
print_debug("\r\n");
print_debug_hex8(j);
print_debug(": ");
}
status = smbus_read_byte(device, j);
if (status < 0) {
print_debug("bad device\r\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
print_debug("\r\n");
}
#if 0
device = ctrl->channel1[i];
if (device) {
int j;
print_debug("dimm: ");
print_debug_hex8(i);
print_debug(".1: ");
print_debug_hex8(device);
for(j = 0; j < 256; j++) {
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
print_debug("\r\n");
print_debug_hex8(j);
print_debug(": ");
}
status = smbus_read_byte(device, j);
if (status < 0) {
print_debug("bad device\r\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
print_debug("\r\n");
}
#endif
}
}
static void dump_smbus_registers(void)
{
int i;
print_debug("\r\n");
for(i = 1; i < 0x80; i++) {
unsigned device;
device = i;
int j;
print_debug("smbus: ");
print_debug_hex8(device);
for(j = 0; j < 256; j++) {
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
print_debug("\r\n");
print_debug_hex8(j);
print_debug(": ");
}
status = smbus_read_byte(device, j);
if (status < 0) {
print_debug("bad device\r\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
print_debug("\r\n");
}
}
#endif

119
src/northbridge/intel/855pm/northbridge.c
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@ -1,119 +0,0 @@
#include <console/console.h>
#include <arch/io.h>
#include <stdint.h>
#include <mem.h>
#include <part/sizeram.h>
#include <device/device.h>
#include <device/pci.h>
#include <stdlib.h>
#include <string.h>
#include <bitops.h>
#include "chip.h"
struct mem_range *sizeram(void)
{
static struct mem_range mem[4];
/* the units of tolm are 64 KB */
/* the units of drb16 are 64 MB */
uint16_t tolm, remapbase, remaplimit, drb16;
uint16_t tolm_r, remapbase_r, remaplimit_r;
uint8_t drb;
int remap_high;
device_t dev;
dev = dev_find_slot(0, 0); // d0f0
if (!dev) {
printk_err("Cannot find PCI: 0:0\n");
return 0;
}
/* Calculate and report the top of low memory and
* any remapping.
*/
/* Test if the remap memory high option is set */
remap_high = 0;
// if(get_option(&remap_high, "remap_memory_high")){
// remap_high = 0;
// }
printk_debug("remap_high is %d\n", remap_high);
/* get out the value of the highest DRB. This tells the end of
* physical memory. The units are ticks of 64 MB i.e. 1 means
* 64 MB.
*/
drb = pci_read_config8(dev, 0x67);
drb16 = (uint16_t)drb;
if(remap_high && (drb16 > 0x08)) {
/* We only come here if we have at least 512MB of memory,
* so it is safe to hard code tolm.
* 0x2000 means 512MB
*/
tolm = 0x2000;
/* i.e 0x40 * 0x40 is 0x1000 which is 4 GB */
if(drb16 > 0x0040) {
/* There is more than 4GB of memory put
* the remap window at the end of ram.
*/
remapbase = drb16;
remaplimit = remapbase + 0x38;
}
else {
remapbase = 0x0040;
remaplimit = remapbase + (drb16-8);
}
}
else {
tolm = (uint16_t)((dev_root.resource[1].base >> 16)&0x0f800);
if((tolm>>8) >= (drb16<<2)) {
tolm = (drb16<<10);
remapbase = 0x3ff;
remaplimit = 0;
}
else {
remapbase = drb16;
remaplimit = remapbase + ((0x0040-(tolm>>10))-1);
}
}
/* Write the ram configruation registers,
* preserving the reserved bits.
*/
tolm_r = pci_read_config16(dev, 0xc4);
tolm |= (tolm_r & 0x7ff);
pci_write_config16(dev, 0xc4, tolm);
remapbase_r = pci_read_config16(dev, 0xc6);
remapbase |= (remapbase_r & 0xfc00);
pci_write_config16(dev, 0xc6, remapbase);
remaplimit_r = pci_read_config16(dev, 0xc8);
remaplimit |= (remaplimit_r & 0xfc00);
pci_write_config16(dev, 0xc8, remaplimit);
#if 0
printk_debug("mem info tolm = %x, drb = %x, pci_memory_base = %x, remap = %x-%x\n",tolm,drb,pci_memory_base,remapbase,remaplimit);
#endif
mem[0].basek = 0;
mem[0].sizek = 640;
mem[1].basek = 768;
/* Convert size in 64K bytes to size in K bytes */
mem[1].sizek = (tolm << 6) - mem[1].basek;
mem[2].basek = 0;
mem[2].sizek = 0;
if ((drb << 16) > (tolm << 6)) {
/* We don't need to consider the remap window
* here because we put it immediately after the
* rest of ram.
* All we must do is calculate the amount
* of unused memory and report it at 4GB.
*/
mem[2].basek = 4096*1024;
mem[2].sizek = (drb << 16) - (tolm << 6);
}
mem[3].basek = 0;
mem[3].sizek = 0;
return mem;
}
struct chip_operations northbridge_intel_855pm_control = {
.name = "intel 855pm Northbridge",
};

2091
src/northbridge/intel/855pm/raminit.c
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11
src/northbridge/intel/855pm/raminit.h
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#ifndef RAMINIT_H
#define RAMINIT_H
#define DIMM_SOCKETS 4
struct mem_controller {
device_t d0;
uint16_t channel0[DIMM_SOCKETS];
};
#endif /* RAMINIT_H */

18
src/northbridge/intel/855pm/reset_test.c
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/* Convert to C by yhlu */
#define MCH_DRC 0x7c
#define DRC_DONE (1 << 29)
/* If I have already booted once skip a bunch of initialization */
/* To see if I have already booted I check to see if memory
* has been enabled.
*/
static int bios_reset_detected(void) {
uint32_t dword;
dword = pci_read_config32(PCI_DEV(0, 0, 0), MCH_DRC);
if( (dword & DRC_DONE) != 0 ) {
return 1;
}
return 0;
}