soc/intel/common: Add reset_prepare() for common reset
Some Intel SoC may need preparation before reset can be properly handled. Add callback that chip/soc code can implement. BUG=chrome-os-partner:55055 Change-Id: I45857838e1a306dbcb9ed262b55e7db88a8944e5 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15720 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -10,5 +10,6 @@ void soft_reset(void);
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void cpu_reset(void);
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/* Some Intel SoCs use a special reset that is specific to SoC */
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void global_reset(void);
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/* Some Intel SoCs may need to prepare/wait before reset */
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void reset_prepare(void);
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#endif
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@ -25,8 +25,17 @@
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#define RST_CPU (1 << 2)
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#define SYS_RST (1 << 1)
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#ifdef __ROMCC__
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#define WEAK
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#else
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#define WEAK __attribute__((weak))
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#endif
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void WEAK reset_prepare(void) { /* do nothing */ }
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void hard_reset(void)
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{
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reset_prepare();
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/* S0->S5->S0 trip. */
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outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT);
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while (1)
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@ -35,6 +44,7 @@ void hard_reset(void)
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void soft_reset(void)
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{
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reset_prepare();
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/* PMC_PLTRST# asserted. */
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outb(RST_CPU | SYS_RST, RST_CNT);
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while (1)
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@ -43,6 +53,7 @@ void soft_reset(void)
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void cpu_reset(void)
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{
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reset_prepare();
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/* Sends INIT# to CPU */
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outb(RST_CPU, RST_CNT);
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while (1)
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