From 640f549eacc365745acd32e78340c225b496af52 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Fri, 19 Mar 2021 11:51:27 -0500 Subject: [PATCH] mb/purism/librem_mini: Drop superfluous devices from devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The 'device pci 00.0 on end' entries are not necessary for socketed devices unless a chip driver needs to be bound to a device, so remove them from the devicetree. Also remove the `drivers/wifi/generic` chip driver as it was not necessary either. Change-Id: Id5f2e34d98b236f9cfac9f0afd8a8017e349603f Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/51663 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner Reviewed-by: Tim Wawrzynczak Reviewed-by: Angel Pons --- .../purism/librem_cnl/variants/librem_mini/devicetree.cb | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index 8fb84ce581..69d1b423bd 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -187,10 +187,7 @@ chip soc/intel/cannonlake device pci 1c.4 off end # PCI Express Port 5 device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 on # PCI Express Port 8 - chip drivers/wifi/generic - device pci 00.0 on end # x1 M.2/E 2230 (WLAN) - end + device pci 1c.7 on # PCI Express Port 8 -- x1 M.2/E 2230 (WLAN) register "PcieRpSlotImplemented[7]" = "1" register "PcieRpEnable[7]" = "1" register "PcieRpLtrEnable[7]" = "1" @@ -207,8 +204,7 @@ chip soc/intel/cannonlake end device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on # PCI Express Port 13 - device pci 00.0 on end # x4 M.2/M 2280 (NVMe) + device pci 1d.4 on # PCI Express Port 13 -- x4 M.2/M 2280 (NVMe) register "PcieRpSlotImplemented[12]" = "1" register "PcieRpEnable[12]" = "1" register "PcieRpLtrEnable[12]" = "1"