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soc/intel/jasperlake: correct IRQ routing Jasper Lake 

Current Interrupt setting use 2nd parameters as device function number.
Correct as interrupt pin number according to _PRT package format.
{Address, pin, Source, Source index}

Reference:
- ACPI spec 6.2.13 _PRT

BUG=None
BRANCH=None
TEST=Build and boot JSLRVP Verify Interrupt mappings are same as PCI
INTR(0x3C) register and no interrupt storm is seen

Change-Id: I21462c6befea310a49eecf9ad1b5c8770eccd5bd
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41404
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Ronak Kanabar 2020-05-14 16:21:18 +05:30 committed by Subrata Banik
parent 56f5cc7ee3
commit 641221c0a1
2 changed files with 91 additions and 145 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

178
src/soc/intel/jasperlake/acpi/pci_irqs.asl
View File

@ -3,119 +3,103 @@
#include <soc/irq.h> #include <soc/irq.h>
Name (PICP, Package () { Name (PICP, Package () {
/* cAVS, SMBus, GbE, Northpeak */ Package(){0x001FFFFF, 0, 0, PCH_IRQ_16 },
Package(){0x001FFFFF, 3, 0, cAVS_INTA_IRQ }, Package(){0x001FFFFF, 1, 0, PCH_IRQ_17 },
Package(){0x001FFFFF, 4, 0, SMBUS_INTB_IRQ }, Package(){0x001FFFFF, 2, 0, PCH_IRQ_18 },
Package(){0x001FFFFF, 6, 0, GbE_INTC_IRQ }, Package(){0x001FFFFF, 3, 0, PCH_IRQ_19 },
Package(){0x001FFFFF, 7, 0, TRACE_HUB_INTD_IRQ },
/* SerialIo */
Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ },
Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ },
Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ }, Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ },
Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ }, Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ },
/* PCI Express Port 1-8 */
Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ }, Package(){0x001CFFFF, 0, 0, PCH_IRQ_16 },
Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ }, Package(){0x001CFFFF, 1, 0, PCH_IRQ_17 },
Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ }, Package(){0x001CFFFF, 2, 0, PCH_IRQ_18 },
Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ }, Package(){0x001CFFFF, 3, 0, PCH_IRQ_19 },
Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ },
Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ }, Package(){0x001AFFFF, 0, 0, PCH_IRQ_16 },
Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ },
Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ },
/* eMMC */
Package(){0x001AFFFF, 0, 0, eMMC_IRQ },
/* SerialIo */
Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ }, Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ },
Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ }, Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ },
Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ }, Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ },
/* SATA controller */
Package(){0x0017FFFF, 0, 0, SATA_IRQ }, Package(){0x0017FFFF, 0, 0, PCH_IRQ_16 },
/* CSME (HECI, IDE-R, Keyboard and Text redirection */
Package(){0x0016FFFF, 0, 0, HECI_1_IRQ }, Package(){0x0016FFFF, 0, 0, PCH_IRQ_16 },
Package(){0x0016FFFF, 1, 0, HECI_2_IRQ }, Package(){0x0016FFFF, 1, 0, PCH_IRQ_17 },
Package(){0x0016FFFF, 2, 0, IDER_IRQ }, Package(){0x0016FFFF, 2, 0, PCH_IRQ_18 },
Package(){0x0016FFFF, 3, 0, KT_IRQ }, Package(){0x0016FFFF, 3, 0, PCH_IRQ_19 },
Package(){0x0016FFFF, 4, 0, HECI_3_IRQ },
Package(){0x0016FFFF, 5, 0, HECI_4_IRQ },
/* SerialIo */
Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ }, Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },
Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ }, Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },
Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ }, Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },
Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ }, Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },
/* D20: xHCI, OTG, SRAM, CNVi WiFi, SD */
Package(){0x0014FFFF, 0, 0, XHCI_IRQ }, Package(){0x0014FFFF, 0, 0, PCH_IRQ_16 },
Package(){0x0014FFFF, 1, 0, OTG_IRQ }, Package(){0x0014FFFF, 1, 0, PCH_IRQ_17 },
Package(){0x0014FFFF, 2, 0, PMC_SRAM_IRQ }, Package(){0x0014FFFF, 2, 0, PCH_IRQ_18 },
Package(){0x0014FFFF, 3, 0, CNViWIFI_IRQ }, Package(){0x0014FFFF, 3, 0, PCH_IRQ_19 },
Package(){0x0014FFFF, 5, 0, SD_IRQ },
/* SerialIo */ Package(){0x0012FFFF, 1, 0, LPSS_SPI2_IRQ },
Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ },
/* SA IGFX Device */
Package(){0x0002FFFF, 0, 0, IGFX_IRQ },
/* SA Thermal Device */
Package(){0x0004FFFF, 0, 0, SA_THERMAL_IRQ },
/* SA IPU Device */
Package(){0x0005FFFF, 0, 0, IPU_IRQ },
/* SA GNA Device */ /* SA GNA Device */
Package(){0x0008FFFF, 0, 0, GNA_IRQ }, Package(){0x0008FFFF, 0, 0, PCH_IRQ_16 },
/* SA IPU Device */
Package(){0x0005FFFF, 0, 0, PCH_IRQ_16 },
/* SA Thermal Device */
Package(){0x0004FFFF, 0, 0, PCH_IRQ_16 },
/* SA IGFX Device */
Package(){0x0002FFFF, 0, 0, PCH_IRQ_16 },
}) })
Name (PICN, Package () { Name (PICN, Package () {
/* D31: cAVS, SMBus, GbE, Northpeak */ Package () { 0x001FFFFF, 0, 0, PCH_IRQ11 },
Package () { 0x001FFFFF, 3, 0, 11 }, Package () { 0x001FFFFF, 1, 0, PCH_IRQ10 },
Package () { 0x001FFFFF, 4, 0, 10 }, Package () { 0x001FFFFF, 2, 0, PCH_IRQ11 },
Package () { 0x001FFFFF, 6, 0, 11 }, Package () { 0x001FFFFF, 3, 0, PCH_IRQ11 },
Package () { 0x001FFFFF, 7, 0, 11 },
/* D30: SerialIo */ Package () { 0x001EFFFF, 0, 0, PCH_IRQ11 },
Package () {0x001EFFFF, 0, 0, 11 }, Package () { 0x001EFFFF, 1, 0, PCH_IRQ10 },
Package () {0x001EFFFF, 1, 0, 10 }, Package () { 0x001EFFFF, 2, 0, PCH_IRQ11 },
Package () {0x001EFFFF, 2, 0, 11 }, Package () { 0x001EFFFF, 3, 0, PCH_IRQ11 },
Package () {0x001EFFFF, 3, 0, 11 },
/* D28: PCI Express Port 1-8 */ Package () { 0x001CFFFF, 0, 0, PCH_IRQ11 },
Package () { 0x001CFFFF, 0, 0, 11 }, Package () { 0x001CFFFF, 1, 0, PCH_IRQ10 },
Package () { 0x001CFFFF, 1, 0, 10 }, Package () { 0x001CFFFF, 2, 0, PCH_IRQ11 },
Package () { 0x001CFFFF, 2, 0, 11 }, Package () { 0x001CFFFF, 3, 0, PCH_IRQ11 },
Package () { 0x001CFFFF, 3, 0, 11 },
Package () { 0x001CFFFF, 4, 0, 11 }, Package () { 0x001AFFFF, 0, 0, PCH_IRQ11 },
Package () { 0x001CFFFF, 5, 0, 10 },
Package () { 0x001CFFFF, 6, 0, 11 }, Package () { 0x0019FFFF, 0, 0, PCH_IRQ11 },
Package () { 0x001CFFFF, 7, 0, 11 }, Package () { 0x0019FFFF, 1, 0, PCH_IRQ10 },
/* D26: eMMC */ Package () { 0x0019FFFF, 2, 0, PCH_IRQ11 },
Package(){0x001AFFFF, 0, 0, 11 },
/* D25: SerialIo */ Package () { 0x0017FFFF, 0, 0, PCH_IRQ11 },
Package () {0x0019FFFF, 0, 0, 11 },
Package () {0x0019FFFF, 1, 0, 10 }, Package () { 0x0016FFFF, 0, 0, PCH_IRQ11 },
Package () {0x0019FFFF, 2, 0, 11 }, Package () { 0x0016FFFF, 1, 0, PCH_IRQ10 },
/* D23: SATA controller */ Package () { 0x0016FFFF, 2, 0, PCH_IRQ11 },
Package () { 0x0017FFFF, 0, 0, 11 }, Package () { 0x0016FFFF, 3, 0, PCH_IRQ11 },
/* D22: CSME (HECI, IDE-R, KT redirection */
Package () { 0x0016FFFF, 0, 0, 11 }, Package () { 0x0015FFFF, 0, 0, PCH_IRQ11 },
Package () { 0x0016FFFF, 1, 0, 10 }, Package () { 0x0015FFFF, 1, 0, PCH_IRQ10 },
Package () { 0x0016FFFF, 2, 0, 11 }, Package () { 0x0015FFFF, 2, 0, PCH_IRQ11 },
Package () { 0x0016FFFF, 3, 0, 11 }, Package () { 0x0015FFFF, 3, 0, PCH_IRQ11 },
Package () { 0x0016FFFF, 4, 0, 11 },
Package () { 0x0016FFFF, 5, 0, 11 }, Package () { 0x0014FFFF, 0, 0, PCH_IRQ11 },
/* D21: SerialIo */ Package () { 0x0014FFFF, 1, 0, PCH_IRQ10 },
Package () {0x0015FFFF, 0, 0, 11 }, Package () { 0x0014FFFF, 2, 0, PCH_IRQ11 },
Package () {0x0015FFFF, 1, 0, 10 }, Package () { 0x0014FFFF, 3, 0, PCH_IRQ11 },
Package () {0x0015FFFF, 2, 0, 11 },
Package () {0x0015FFFF, 3, 0, 11 }, Package () { 0x0012FFFF, 1, 0, PCH_IRQ10 },
/* D20: xHCI, OTG, SRAM, CNVi WiFi, SD */
Package () { 0x0014FFFF, 0, 0, 11 },
Package () { 0x0014FFFF, 1, 0, 10 },
Package () { 0x0014FFFF, 2, 0, 11 },
Package () { 0x0014FFFF, 3, 0, 11 },
Package () { 0x0014FFFF, 5, 0, 11 },
/* D18: SerialIo */
Package () {0x0012FFFF, 6, 0, 11 },
/* SA IGFX Device */
Package () {0x0002FFFF, 0, 0, 11 },
/* SA Thermal Device */
Package () { 0x0004FFFF, 0, 0, 11 },
/* SA IPU Device */
Package () { 0x0005FFFF, 0, 0, 11 },
/* SA GNA Device */ /* SA GNA Device */
Package () { 0x0008FFFF, 0, 0, 11 }, Package () { 0x0008FFFF, 0, 0, PCH_IRQ11 },
/* SA IPU Device */
Package () { 0x0005FFFF, 0, 0, PCH_IRQ11 },
/* SA Thermal Device */
Package () { 0x0004FFFF, 0, 0, PCH_IRQ11 },
/* SA IGFX Device */
Package () { 0x0002FFFF, 0, 0, PCH_IRQ11 },
}) })
Method (_PRT) Method (_PRT)

58
src/soc/intel/jasperlake/include/soc/irq.h
View File

@ -9,7 +9,7 @@
#define PCH_IRQ10 10 #define PCH_IRQ10 10
#define PCH_IRQ11 11 #define PCH_IRQ11 11
/* LPSS Devices */ /* LPSS Device IRQs */
#define LPSS_I2C0_IRQ 16 #define LPSS_I2C0_IRQ 16
#define LPSS_I2C1_IRQ 17 #define LPSS_I2C1_IRQ 17
#define LPSS_I2C2_IRQ 18 #define LPSS_I2C2_IRQ 18
@ -23,52 +23,14 @@
#define LPSS_UART1_IRQ 21 #define LPSS_UART1_IRQ 21
#define LPSS_UART2_IRQ 34 #define LPSS_UART2_IRQ 34
/* PCI D:31 F:x */ /* PCI shared IRQs */
#define cAVS_INTA_IRQ 16 #define PCH_IRQ_16 16
#define SMBUS_INTA_IRQ 16 #define PCH_IRQ_17 17
#define SMBUS_INTB_IRQ 17 #define PCH_IRQ_18 18
#define GbE_INTA_IRQ 16 #define PCH_IRQ_19 19
#define GbE_INTC_IRQ 18 #define PCH_IRQ_20 20
#define TRACE_HUB_INTA_IRQ 16 #define PCH_IRQ_21 21
#define TRACE_HUB_INTD_IRQ 19 #define PCH_IRQ_22 22
#define PCH_IRQ_23 23
/* PCI D:28 F:x */
#define PCIE_1_IRQ 16
#define PCIE_2_IRQ 17
#define PCIE_3_IRQ 18
#define PCIE_4_IRQ 19
#define PCIE_5_IRQ 16
#define PCIE_6_IRQ 17
#define PCIE_7_IRQ 18
#define PCIE_8_IRQ 19
/* PCI D:26 F:x */
#define eMMC_IRQ 16
/* PCI D:23 F:x */
#define SATA_IRQ 16
/* PCI D:22 F:x */
#define HECI_1_IRQ 16
#define HECI_2_IRQ 17
#define HECI_3_IRQ 16
#define HECI_4_IRQ 19
#define IDER_IRQ 18
#define KT_IRQ 19
/* PCI D:20 F:x */
#define XHCI_IRQ 16
#define OTG_IRQ 17
#define CNViWIFI_IRQ 16
#define SD_IRQ 19
#define PMC_SRAM_IRQ 18
/* PCI D:18 F:x */
#define UFS_IRQ 16
#define IGFX_IRQ 16
#define SA_THERMAL_IRQ 16
#define IPU_IRQ 16
#define GNA_IRQ 16
#endif /* _JSL_IRQ_H_ */ #endif /* _JSL_IRQ_H_ */